/**************************************************************************** * * * file name : io7544.H * * * * Copyright : RENESAS TECHNOLOGY CORPORATION * * * * Version : 1.00 ( 2003-6-16 ) Initial * * : 2.00 ( 2004-6-11 ) add P0 to P3 bit definition * * * *****************************************************************************/ /* note: This data is a freeware that SFR for 7544 Group is described. RENESAS TECHNOLOGY CORPORATION assumes no responsibility for any damage that occurred by this data. */ #ifndef Chip_7544 #define Chip_7544 #endif #pragma language=extended /*=================================== * Special function registers (SFR) *=================================== */ sfr P0 = 0x00000; /* Port P0 */ sfr P0D = 0x00001; /* Port P0 direction register */ sfr P1 = 0x00002; /* Port P1 */ sfr P1D = 0x00003; /* Port P1 direction register */ sfr P2 = 0x00004; /* Port P2 */ sfr P2D = 0x00005; /* Port P2 direction register */ sfr P3 = 0x00006; /* Port P3 */ sfr P3D = 0x00007; /* Port P3 direction register */ sfr PULL = 0x00016; /* Pull-up control register */ sfr P1P3C = 0x00017; /* Port P1P3 control register */ sfr TBRB = 0x00018; /* Transmit /Receive buffer register */ sfr SIOSTS = 0x00019; /* Serial I/O status register */ sfr SIOCON = 0x0001a; /* Serial I/O control register */ sfr UARTCON = 0x0001b; /* UART control register */ sfr BRG = 0x0001c; /* Baud rate generator */ sfr TAM = 0x0001d; /* Timer A mode register */ sfr TAL = 0x0001e; /* Timer A (low-order) */ sfr TAH = 0x0001f; /* Timer A (high-order) */ sfr PRE1 = 0x00028; /* Prescaler 1 */ sfr T1 = 0x00029; /* Timer 1 */ sfr TXM = 0x0002b; /* Timer X mode register */ sfr PREX = 0x0002c; /* Prescaler X */ sfr TX = 0x0002d; /* Timer X */ sfr TCSS1 = 0x0002e; /* Timer count source set register 1 */ sfr TCSS2 = 0x0002f; /* Timer count source set register 2 */ sfr ADCON = 0x00034; /* A-D control register */ sfr AD = 0x00035; /* A-D register */ sfr MISRG = 0x00038; /* MISRG */ sfr WDTCON = 0x00039; /* Watchdog timer control register */ sfr INTEDGE = 0x0003a; /* Interrupt edge selection register */ sfr CPUM = 0x0003b; /* CPU mode register */ sfr IREQ1 = 0x0003c; /* Interrupt request register 1 */ sfr IREQ2 = 0x0003d; /* Interrupt request register 2 */ sfr ICON1 = 0x0003e; /* Interrupt control register 1 */ sfr ICON2 = 0x0003f; /* Interrupt control register 2 */ #ifdef __IAR_SYSTEMS_ICC__ /*------------------------------------------------------ Port P0 register ------------------------------------------------------*/ bit P0_0 = P0.0; /* P0 register bit0 */ bit P0_1 = P0.1; /* P0 register bit1 */ bit P0_2 = P0.2; /* P0 register bit2 */ bit P0_3 = P0.3; /* P0 register bit3 */ bit P0_4 = P0.4; /* P0 register bit4 */ bit P0_5 = P0.5; /* P0 register bit5 */ bit P0_6 = P0.6; /* P0 register bit6 */ bit P0_7 = P0.7; /* P0 register bit7 */ /*------------------------------------------------------ Port P1 register ------------------------------------------------------*/ bit P1_0 = P1.0; /* P1 register bit0 */ bit P1_1 = P1.1; /* P1 register bit1 */ bit P1_2 = P1.2; /* P1 register bit2 */ bit P1_3 = P1.3; /* P1 register bit3 */ bit P1_4 = P1.4; /* P1 register bit4 */ /*------------------------------------------------------ Port P2 register ------------------------------------------------------*/ bit P2_0 = P2.0; /* P2 register bit0 */ bit P2_1 = P2.1; /* P2 register bit1 */ bit P2_2 = P2.2; /* P2 register bit2 */ bit P2_3 = P2.3; /* P2 register bit3 */ bit P2_4 = P2.4; /* P2 register bit4 */ bit P2_5 = P2.5; /* P2 register bit5 */ /*------------------------------------------------------ Port P3 register ------------------------------------------------------*/ bit P3_0 = P3.0; /* P3 register bit0 */ bit P3_1 = P3.1; /* P3 register bit1 */ bit P3_2 = P3.2; /* P3 register bit2 */ bit P3_3 = P3.3; /* P3 register bit3 */ bit P3_4 = P3.4; /* P3 register bit4 */ bit P3_5 = P3.5; /* P3 register bit5 */ bit P3_6 = P3.6; /* P3 register bit6 */ bit P3_7 = P3.7; /* P3 register bit7 */ #endif