COP8 "C" COMPILER V3.51 25-Mar-2002 PAGE 1 #pragma option f0 /* remove page breaks from listing file */ /* * COP8C Code Development System * Tutorial Example * IOPORT.C * This code may be adapted for any purpose * when used with the COP8C Code Development * System. No warranty is implied or given * as to their usability for any purpose. * * (c) Copyright 2000 Byte Craft Limited * 421 King St.N., Waterloo, ON, Canada, N2J 4E4 * VOICE: 1 (519) 888 6911 * FAX : 1 (519) 746 6751 * email: support@bytecraft.com * * REVISION HISTORY * v1.00 AL 01/2000 Initial Version. */ #include #ifndef __COP8C_H 0007 #define __COP8C_H /* COP8C Code Development System Header file for National Semiconductor: COP8CBR This code may be adapted for any purpose when used with the COP8C Code Development System. No warranty is implied or given as to their usability for any purpose. (c) Copyright 2000 Byte Craft Limited 421 King St.N., Waterloo, ON, Canada, N2J 4E4 VOICE: 1 (519) 888 6911 FAX : 1 (519) 746 6751 email: support@bytecraft.com REVISION HISTORY V1.00 AL 01/00 Initial version */ /* PRAGMA HAS */ #pragma has 888; #pragma has SREG; 00FE #pragma regb BREG; 00EF #pragma regix IX; 00EF #pragma regac AC; 00FC #pragma portrw X @ 0xFC; 00FD #pragma portrw SP @ 0xFD; 00FE #pragma portrw B @ 0xFE; 00FF #pragma portrw S @ 0xFF; /* MEMORY INFO */ 8000 #define ROM_SIZE 32768 0200 #define CODE_START 0x200 0200 7DFF #pragma memory ROM [ROM_SIZE - CODE_START -1] @ CODE_START; 0040 #define STACK_SIZE 0x40 0008 #define RAM_BANK0_START 8 /* leave space for compiler temps 0x0-0x7 */ 0028 #define RAM_BANK0_SIZE 0x70-RAM_BANK0_START-STACK_SIZE 0100 #define RAM_BANK1_START 0x100 0200 #define RAM_BANK2_START 0x200 0300 #define RAM_BANK3_START 0x300 0400 #define RAM_BANK4_START 0x400 0500 #define RAM_BANK5_START 0x500 0600 #define RAM_BANK6_START 0x600 0700 #define RAM_BANK7_START 0x700 0080 #define RAM_BANK1_SIZE 0x80 0080 #define RAM_BANK2_SIZE 0x80 0080 #define RAM_BANK3_SIZE 0x80 0080 #define RAM_BANK4_SIZE 0x80 0080 #define RAM_BANK5_SIZE 0x80 0080 #define RAM_BANK6_SIZE 0x80 0080 #define RAM_BANK7_SIZE 0x80 00F1 #define RAM_REGISTERS_START 0xF1 /* reserve 0xF0 for compiler */ 000B #define RAM_REGISTERS_SIZE 0xFC-RAM_REGISTERS_START 0030 0040 #pragma memory STACK [STACK_SIZE] @ RAM_BANK0_START+RAM_BANK0_SIZE; 0008 0028 #pragma memory RAM bank0 [RAM_BANK0_SIZE] @ RAM_BANK0_START; 0100 0080 #pragma memory RAM bank1 [RAM_BANK1_SIZE] @ RAM_BANK1_START; 0200 0080 #pragma memory RAM bank2 [RAM_BANK2_SIZE] @ RAM_BANK2_START; 0300 0080 #pragma memory RAM bank3 [RAM_BANK3_SIZE] @ RAM_BANK3_START; 0400 0080 #pragma memory RAM bank4 [RAM_BANK4_SIZE] @ RAM_BANK4_START; 0500 0080 #pragma memory RAM bank5 [RAM_BANK5_SIZE] @ RAM_BANK5_START; 0600 0080 #pragma memory RAM bank6 [RAM_BANK6_SIZE] @ RAM_BANK6_START; 0700 0080 #pragma memory RAM bank7 [RAM_BANK7_SIZE] @ RAM_BANK7_START; 077F 0000 #pragma memory LOCAL [0] @ RAM_BANK7_START+RAM_BANK7_SIZE-1; 00F1 000B #pragma memory RAM register [RAM_REGISTERS_SIZE] @ RAM_REGISTERS_START; /* Interrupts */ 01FE #pragma vector __SWI @ 0x1FE; /* Software INTR Instruction */ 01FA #pragma vector __EXT @ 0x1FA; /* External Pin G0 edge */ 01F8 #pragma vector __TIMERT0 @ 0x1F8; /* Timer T0 Underflow */ 01F6 #pragma vector __TIMERT1A @ 0x1F6; /* Timer T1 T1A/Underflow */ 01F4 #pragma vector __TIMERT1B @ 0x1F4; /* Timer T1 T1B */ 01F2 #pragma vector __MICRO @ 0x1F2; /* MICROWIRE/PLUS */ 01EE #pragma vector __UARTR @ 0x1EE; /* UART Recieve */ 01EC #pragma vector __UARTT @ 0x1EC; /* UART Transmit */ 01EA #pragma vector __TIMERT2A @ 0x1EA; /* Timer T2 T2A/Underflow */ 01E8 #pragma vector __TIMERT2B @ 0x1E8; /* Timer T2 T2B */ 01E6 #pragma vector __TIMERT3A @ 0x1E6; /* Timer T3 T3A/Underflow */ 01E4 #pragma vector __TIMERT3B @ 0x1E4; /* Timer T3 T3B */ 01E2 #pragma vector __PORTL @ 0x1E2; /* PortL/wakeup PortL Edge */ 01E0 #pragma vector __VIS @ 0x1E0; /* Default */ /* place the VIS instruction at 0xff */ 00B4 #define VIS_OPCODE 0xb4 00FF #pragma vector INTERRUPT_BRANCH_VECTOR @ 0xFF; 00FF 02 00 void INTERRUPT_BRANCH_VECTOR(void) @ VIS_OPCODE<<8; 00FF B4 00 /* option register bit definitions */ /* #define OPTION_VAL ENABLE_SECURITY | DISABLE_WATCHDOG */ 7FFF #define OPTION_LOCATION 0x7fff 0020 #define SEC_ENABLE 0b00100000 0000 #define SEC_DISABLE 0b00000000 0004 #define WD_DISABLE 0b00000100 0000 #define WD_ENABLE 0b00000000 0002 #define HALT_DISABLE 0b00000010 0000 #define HALT_ENABLE 0b00000000 0001 #define FLEX_FLASH 0b00000001 0000 #define FLEX_ROM 0b00000000 #ifdef OPTION_VAL /*#define OPTION_VAL SEC_DISABLE | WD_ENABLE | HALT_DISABLE | FLEX_FLASH */ #pragma ECON @ OPTION_LOCATION = OPTION_VAL; #endif /* ECON_VAL */ /* PORTE */ 0090 #pragma portrw PORTE @ 0x90; /* PORTE data register */ 0090 #pragma portrw PORTED @ 0x90; /* PORTE data register */ 0091 #pragma portrw PORTEC @ 0x91; /* PORTE configuration register */ 0092 #pragma portr PORTEP @ 0x92; /* PORTE input pins */ /* PORTF */ 0094 #pragma portrw PORTF @ 0x94; /* PORTF data register */ 0094 #pragma portrw PORTFD @ 0x94; /* PORTF data register */ 0095 #pragma portrw PORTFC @ 0x95; /* PORTF configuration register */ 0096 #pragma portr PORTFP @ 0x96; /* PORTF input pins */ /* PORTA */ 00A0 #pragma portrw PORTA @ 0xA0; /* PORTA data register */ 00A0 #pragma portrw PORTAD @ 0xA0; /* PORTA data register */ 00A1 #pragma portrw PORTAC @ 0xA1; /* PORTA configuration register */ 00A2 #pragma portr PORTAP @ 0xA2; /* PORTA input pins */ /* PORTB */ 00A4 #pragma portrw PORTB @ 0xA4; /* PORTB data register */ 00A4 #pragma portrw PORTBD @ 0xA4; /* PORTB data register */ 00A5 #pragma portrw PORTBC @ 0xA5; /* PORTB configuration register */ 00A6 #pragma portr PORTBP @ 0xA6; /* PORTB input pins */ /* HSTCR */ 00AD #pragma portr TINTA @ 0xAD; /* high speed interrupt A */ 00AE #pragma portr TINTB @ 0xAE; /* high speed interrupt b */ 00AF #pragma portrw HSTCR @ 0xAF; /* high speed timer control register */ 0001 #define T3HS 1 0000 #define T2HS 0 /* PORTL */ 00D0 #pragma portrw PORTL @ 0xD0; /* PORTL data register */ 00D0 #pragma portrw PORTLD @ 0xD0; /* PORTL data register */ 00D1 #pragma portrw PORTLC @ 0xD1; /* PORTL configuration register */ 00D2 #pragma portr PORTLP @ 0xD2; /* PORTL input pins */ /* PORTG */ 00D4 #pragma portrw PORTG @ 0xD4; /* PORTG data register */ 00D4 #pragma portrw PORTGD @ 0xD4; /* PORTG data register */ 00D5 #pragma portrw PORTGC @ 0xD5; /* PORTG configuration register */ 00D6 #pragma portr PORTGP @ 0xD6; /* PORTG input pins */ /* PORTC */ 00D8 #pragma portrw PORTC @ 0xD8; /* PORTC data register */ 00D8 #pragma portrw PORTCD @ 0xD8; /* PORTC data register */ 00D9 #pragma portrw PORTCC @ 0xD9; /* PORTC configuration register */ 00DA #pragma portr PORTCP @ 0xDA; /* PORTC input pins */ /* PORTD */ 00DC #pragma portrw PORTD @ 0xDC; /* PORTD data register */ 00DC #pragma portrw PORTDD @ 0xDC; /* PORTD data register */ /* control registers */ 00EE #pragma portrw CNTRL @ 0xEE; /* CNTRL control register */ 0007 #define T1C3 7 /* timer T1 mode control bit */ 0006 #define T1C2 6 /* timer T1 mode control bit */ 0005 #define T1C1 5 /* timer T1 mode control bit */ 0004 #define T1C0 4 /* timer T1 mode control bit */ 0003 #define MSEL 3 /* selects G5 and G4 as MICROWIRE/PLUS signals SK and SO */ 0002 #define IEDG 2 /* external interrupt edge polarity select */ 0001 #define SL1 1 /* select MICROWIRE/PLUS clock divide */ 0000 #define SL0 0 /* select MICROWIRE/PLUS clock divide */ 00EF #pragma portrw PSW @ 0xEF; /* PSW register */ 0007 #define HC 7 /* half carry flag */ 0006 #define C 6 /* carry flag */ 0005 #define T1PND 5 /* timer T1 interrupt pending flag */ 0005 #define T1PNDA 5 /* timer T1 interrupt pending flag */ 0004 #define T1ENA 4 /* timer T1 interrupt enable for timer underflow or T1A */ 0003 #define EXPND 3 /* external interrupt pending */ 0002 #define BUSY 2 /* MICROWIRE/PLUS busy shifting flag */ 0001 #define EXEN 1 /* enable external interrupt */ 0000 #define GIE 0 /* global interrupt enable */ 00E8 #pragma portrw ICNTRL @ 0xE8; /* ICNTRL register */ 0006 #define LPEN 6 /* PORTL interrupt enable */ 0005 #define T0PND 5 /* timer T0 interrupt pending */ 0004 #define T0EN 4 /* timer T0 interrupt enable */ 0003 #define uWPND 3 /* MICROWIRE/PLUS interrupt pending */ 0002 #define uWEN 2 /* enable MICROWIRE/PLUS interrupt */ 0001 #define T1PNDB 1 /* timer T1 interrupt pending flag for T1B capture edge */ 0000 #define T1ENB 0 /* timer T1 interrupt enable for T1B input capture edge */ /* timer 1 */ 00EA #pragma portrw TMRLO @ 0xEA; /* timer T1 lower byte */ 00EB #pragma portrw TMRHI @ 0xEB; /* timer T1 upper byte */ 00EC #pragma portrw T1RALO @ 0xEC; /* timer T1 autoload register T1RA lower byte */ 00ED #pragma portrw T1RAHI @ 0xED; /* timer T1 autoload register T1RA upper byte */ 00E6 #pragma portrw T1RBLO @ 0xE6; /* timer T1 autoload register T1RB lower byte */ 00E7 #pragma portrw T1RBHI @ 0xE7; /* timer T1 autoload register T1RB upper byte */ /* timer 2 */ 00C6 #pragma portrw T2CNTRL @ 0xC6; /* timer T2 control register */ 0007 #define T2C3 7 /* timer T2 mode control bit */ 0006 #define T2C2 6 /* timer T2 mode control bit */ 0005 #define T2C1 5 /* timer T2 mode control bit */ 0004 #define T2C0 4 /* timer T2 mode control bit */ 0003 #define T2PNDA 3 /* timer T2 interrupt pending flag */ 0002 #define T2ENA 2 /* timer T2 interrupt enable for timer underflow or T2A */ 0001 #define T2PNDB 1 /* timer T2 interrupt pending flag */ 0000 #define T2ENB 0 /* timer T2 interrupt enable for T2B input capture edge */ 00C0 #pragma portrw TMR2LO @ 0xC0; /* timer T2 lower byte */ 00C1 #pragma portrw TMR2HI @ 0xC1; /* timer T2 upper byte */ 00C2 #pragma portrw T2RALO @ 0xC2; /* timer T2 autoload register T2RA lower byte */ 00C3 #pragma portrw T2RAHI @ 0xC3; /* timer T2 autoload register T2RA upper byte */ 00C4 #pragma portrw T2RBLO @ 0xC4; /* timer T2 autoload register T2RB lower byte */ 00C5 #pragma portrw T2RBHI @ 0xC5; /* timer T2 autoload register T2RB upper byte */ /* timer 3 */ 00B6 #pragma portrw T3CNTRL @ 0xB6; /* timer T3 control register */ 0007 #define T3C3 7 /* timer T3 mode control bit */ 0006 #define T3C2 6 /* timer T3 mode control bit */ 0005 #define T3C1 5 /* timer T3 mode control bit */ 0004 #define T3C0 4 /* timer T3 mode control bit */ 0003 #define T3PNDA 3 /* timer T3 interrupt pending flag */ 0002 #define T3ENA 2 /* timer T3 interrupt enable for timer underflow or T3A */ 0001 #define T3PNDB 1 /* timer T3 interrupt pending flag */ 0000 #define T3ENB 0 /* timer T3 interrupt enable for T3B input capture edge */ 00B0 #pragma portrw TMR3LO @ 0xB0; /* timer T3 lower byte */ 00B1 #pragma portrw TMR3HI @ 0xB1; /* timer T3 upper byte */ 00B2 #pragma portrw T3RALO @ 0xB2; /* timer T3 autoload register T3RA lower byte */ 00B3 #pragma portrw T3RAHI @ 0xB3; /* timer T3 autoload register T3RA upper byte */ 00B4 #pragma portrw T3RBLO @ 0xB4; /* timer T3 autoload register T3RB lower byte */ 00B5 #pragma portrw T3RBHI @ 0xB5; /* timer T3 autoload register T3RB upper byte */ 00E9 #pragma portrw SIOR @ 0xE9; /* MICROWIRE/PLUS shift register */ /* ITMR */ 00CF #pragma portrw ITMR @ 0xCF; /* idle timer control register */ 0007 #define LSON 7 /* turns the low speed oscillator on or off */ 0006 #define HSON 6 /* turns the high speed oscillator on or off */ 0005 #define DCEN 5 /* clock idle timer with high speed clock */ 0004 #define CCKSEL 4 /* high speed timer as CPU clock */ 0002 #define ITSEL2 2 /* idle timer period bit */ 0001 #define ITSEL1 1 /* idle timer period bit */ 0000 #define ITSEL0 0 /* idle timer period bit */ /* ENAD */ 00CB #pragma portrw ENAD @ 0xCB; /* A/D converter control register */ 0007 #define ADCH3 7 /* ADC channel select bit */ 0006 #define ADCH2 6 /* ADC channel select bit */ 0005 #define ADCH1 5 /* ADC channel select bit */ 0004 #define ADCH0 4 /* ADC channel select bit */ 0003 #define ADMOD 3 /* places the ADC in single-ended or differential mode */ 0002 #define MUX 2 /* enables the ADC multiplexor output */ 0001 #define PSC 1 /* MCLK divide by 1 or 12 */ 0000 #define ADBSY 0 /* ADC busy (currently converting) */ /* ADRSLTL */ 00CD #pragma portrw ADRSLTL @ 0xCD; /* A/D converter result low */ /* ADRSLTH */ 00CC #pragma portrw ADRSLTH @ 0xCC; /* A/D converter result high */ /* ISPAD */ 00A8 #pragma portrw ISPAD @ 0xA8; /* ISP address register */ /* ISPADLO */ 00A8 #pragma portrw ISPADLO @ 0xA8; /* ISP address register low */ /* ISPADHI */ 00A9 #pragma portrw ISPADHI @ 0xA9; /* ISP address register high */ /* ISPRD */ 00AA #pragma portrw ISPRD @ 0xAA; /* ISP read data register low */ /* ISPWR */ 00AB #pragma portrw ISPWR @ 0xAB; /* ISP write data register low */ /* PGMTIM */ 00E1 #pragma portrw PGMTIM @ 0xE1; /* flash memory write timing register */ /* ISPKEY */ 00E2 #pragma portrw ISPKEY @ 0xE2; /* ISP key register */ /* UART */ 00B8 #pragma portrw TBUF @ 0xB8; /* UART transmit buffer */ 00B9 #pragma portrw RBUF @ 0xB9; /* UART receive buffer */ 00BA #pragma portrw ENU @ 0xBA; /* UART Control and Status */ 0007 #define PEN 7 /* enable / dis-able Parity */ 0006 #define PSEL1 6 /* Parity select bits */ 0005 #define XBIT9 5 /* Program Bit transmission or Selects Parity */ 0005 #define PSEL0 5 /* Program Bit transmission or Selects Parity */ 0004 #define CHL1 4 /* frame format selection */ 0003 #define CHL0 3 /* frame format selection */ 0002 #define ERR 2 /* error Flag */ 0001 #define RBFL 1 /* Byte Received Flag */ 0000 #define TBMT 0 /* Byte Transfered Flag */ 00BB #pragma portrw ENUR @ 0xBB; /* UART Receive Control and Status */ 0007 #define DOE 7 /* Data Overrun error */ 0006 #define FE 6 /* Flag Framing error */ 0005 #define PE 5 /* Parity error */ 0004 #define BD 4 /* flags a line break */ 0003 #define RBIT9 3 /* Ninth bit in UART nine bit mode */ 0002 #define ATTN 2 /* Attention mode enable */ 0001 #define XMTG 1 /* UART transmitting indicator */ 0000 #define RCVG 0 /* Framing error (goes low when RDX goes high) */ 00BC #pragma portrw ENUI @ 0xBC; /* UART register - Interrupt and Clock Source */ 0007 #define STP2 7 /* Sets number of Stop bits to be Transmitted */ 0006 #define BRK 6 /* Holds TDX low to generate a line break */ 0005 #define ETDX 5 /* ETDX - UART Transmit Pin */ 0004 #define SSEL 4 /* UART Mode Select */ 0003 #define XRCLK 3 /* Clock source selection reception */ 0002 #define XTCLK 2 /* Clock source selection transmission */ 0001 #define ERI 1 /* Enable / Disable Receiver interrupt */ 0000 #define ETI 0 /* Enable / Disable Transmiter Interrupt */ 00BD #pragma portrw BAUD @ 0xBD; /* UART baud register */ 00BE #pragma portrw PSR @ 0xBE; /* UART prescale select register */ 00C7 #pragma portrw WDSVR @ 0xC7; /* WATCHDOG service register */ 00C8 #pragma portrw LWKEDG @ 0xC8; /* LMIWU edge select register */ 00C9 #pragma portrw LWKEN @ 0xC9; /* LMIWU enable register */ 00CA #pragma portrw LWKPND @ 0xCA; /* LMIWU pending register */ #endif /* __COP8C_H */ #include #ifndef __PORT_H 0008 #define __PORT_H #endif /* __PORT_H */ /*_ioport_*/ void main(void) { DDR(PORTL,IIIIOIII); /* set PORTL.3 to an output */ 0200 BC D1 08 LD 0D1,#08 0203 98 01 LD A,#001 while(1) /* loop forever */ 0205 9F D0 LD B,#0D0 0207 73 IFBIT 03,[B] 0208 64 CLRA 0209 92 00 IFEQ A,#000 PORTLD.3 = !PORTLD.3; /* toggle the output pin */ 020B 02 JP 0020E 020C 7B SBIT 03,[B] 020D 01 JP 0020F 020E 6B RBIT 03,[B] 020F F3 JP 00203 } /*_ioport_*/ #endif /* __COP8C_C */ __MAIN: 0000 DD 6F LD SP,#06F 0002 AC 02 00 JMPL 00200 SYMBOL TABLE LABEL VALUE LABEL VALUE ADBSY 0000 ADCH0 0004 ADCH1 0005 ADCH2 0006 ADCH3 0007 ADMOD 0003 ADRSLTH 00CC ADRSLTL 00CD ATTN 0002 B 00FE BAUD 00BD BD 0004 BREG Reg 00FE BRK 0006 BUSY 0002 C 0006 CCKSEL 0004 CHL0 0003 CHL1 0004 CNTRL 00EE CODE_START 0200 DCEN 0005 DOE 0007 ENAD 00CB ENU 00BA ENUI 00BC ENUR 00BB ERI 0001 ERR 0002 ETDX 0005 ETI 0000 EXEN 0001 EXPND 0003 FE 0006 FLEX_FLASH 0001 FLEX_ROM 0000 GIE 0000 HALT_DISABLE 0002 HALT_ENABLE 0000 HC 0007 HSON 0006 HSTCR 00AF ICNTRL 00E8 IEDG 0002 IIIIIIII 0000 IIIIIIIO 0001 IIIIIIOI 0002 IIIIIIOO 0003 IIIIIOII 0004 IIIIIOIO 0005 IIIIIOOI 0006 IIIIIOOO 0007 IIIIOIII 0008 IIIIOIIO 0009 IIIIOIOI 000A IIIIOIOO 000B IIIIOOII 000C IIIIOOIO 000D IIIIOOOI 000E IIIIOOOO 000F IIIOIIII 0010 IIIOIIIO 0011 IIIOIIOI 0012 IIIOIIOO 0013 IIIOIOII 0014 IIIOIOIO 0015 IIIOIOOI 0016 IIIOIOOO 0017 IIIOOIII 0018 IIIOOIIO 0019 IIIOOIOI 001A IIIOOIOO 001B IIIOOOII 001C IIIOOOIO 001D IIIOOOOI 001E IIIOOOOO 001F IIOIIIII 0020 IIOIIIIO 0021 IIOIIIOI 0022 IIOIIIOO 0023 IIOIIOII 0024 IIOIIOIO 0025 IIOIIOOI 0026 IIOIIOOO 0027 IIOIOIII 0028 IIOIOIIO 0029 IIOIOIOI 002A IIOIOIOO 002B IIOIOOII 002C IIOIOOIO 002D IIOIOOOI 002E IIOIOOOO 002F IIOOIIII 0030 IIOOIIIO 0031 IIOOIIOI 0032 IIOOIIOO 0033 IIOOIOII 0034 IIOOIOIO 0035 IIOOIOOI 0036 IIOOIOOO 0037 IIOOOIII 0038 IIOOOIIO 0039 IIOOOIOI 003A IIOOOIOO 003B IIOOOOII 003C IIOOOOIO 003D IIOOOOOI 003E IIOOOOOO 003F INTERRUPT_BRANCH_VECTOR 00FF IOIIIIII 0040 IOIIIIIO 0041 IOIIIIOI 0042 IOIIIIOO 0043 IOIIIOII 0044 IOIIIOIO 0045 IOIIIOOI 0046 IOIIIOOO 0047 IOIIOIII 0048 IOIIOIIO 0049 IOIIOIOI 004A IOIIOIOO 004B IOIIOOII 004C IOIIOOIO 004D IOIIOOOI 004E IOIIOOOO 004F IOIOIIII 0050 IOIOIIIO 0051 IOIOIIOI 0052 IOIOIIOO 0053 IOIOIOII 0054 IOIOIOIO 0055 IOIOIOOI 0056 IOIOIOOO 0057 IOIOOIII 0058 IOIOOIIO 0059 IOIOOIOI 005A IOIOOIOO 005B IOIOOOII 005C IOIOOOIO 005D IOIOOOOI 005E IOIOOOOO 005F IOOIIIII 0060 IOOIIIIO 0061 IOOIIIOI 0062 IOOIIIOO 0063 IOOIIOII 0064 IOOIIOIO 0065 IOOIIOOI 0066 IOOIIOOO 0067 IOOIOIII 0068 IOOIOIIO 0069 IOOIOIOI 006A IOOIOIOO 006B IOOIOOII 006C IOOIOOIO 006D IOOIOOOI 006E IOOIOOOO 006F IOOOIIII 0070 IOOOIIIO 0071 IOOOIIOI 0072 IOOOIIOO 0073 IOOOIOII 0074 IOOOIOIO 0075 IOOOIOOI 0076 IOOOIOOO 0077 IOOOOIII 0078 IOOOOIIO 0079 IOOOOIOI 007A IOOOOIOO 007B IOOOOOII 007C IOOOOOIO 007D IOOOOOOI 007E IOOOOOOO 007F ISPAD 00A8 ISPADHI 00A9 ISPADLO 00A8 ISPKEY 00E2 ISPRD 00AA ISPWR 00AB ITMR 00CF ITSEL0 0000 ITSEL1 0001 ITSEL2 0002 LPEN 0006 LSON 0007 LWKEDG 00C8 LWKEN 00C9 LWKPND 00CA MSEL 0003 MUX 0002 OIIIIIII 0080 OIIIIIIO 0081 OIIIIIOI 0082 OIIIIIOO 0083 OIIIIOII 0084 OIIIIOIO 0085 OIIIIOOI 0086 OIIIIOOO 0087 OIIIOIII 0088 OIIIOIIO 0089 OIIIOIOI 008A OIIIOIOO 008B OIIIOOII 008C OIIIOOIO 008D OIIIOOOI 008E OIIIOOOO 008F OIIOIIII 0090 OIIOIIIO 0091 OIIOIIOI 0092 OIIOIIOO 0093 OIIOIOII 0094 OIIOIOIO 0095 OIIOIOOI 0096 OIIOIOOO 0097 OIIOOIII 0098 OIIOOIIO 0099 OIIOOIOI 009A OIIOOIOO 009B OIIOOOII 009C OIIOOOIO 009D OIIOOOOI 009E OIIOOOOO 009F OIOIIIII 00A0 OIOIIIIO 00A1 OIOIIIOI 00A2 OIOIIIOO 00A3 OIOIIOII 00A4 OIOIIOIO 00A5 OIOIIOOI 00A6 OIOIIOOO 00A7 OIOIOIII 00A8 OIOIOIIO 00A9 OIOIOIOI 00AA OIOIOIOO 00AB OIOIOOII 00AC OIOIOOIO 00AD OIOIOOOI 00AE OIOIOOOO 00AF OIOOIIII 00B0 OIOOIIIO 00B1 OIOOIIOI 00B2 OIOOIIOO 00B3 OIOOIOII 00B4 OIOOIOIO 00B5 OIOOIOOI 00B6 OIOOIOOO 00B7 OIOOOIII 00B8 OIOOOIIO 00B9 OIOOOIOI 00BA OIOOOIOO 00BB OIOOOOII 00BC OIOOOOIO 00BD OIOOOOOI 00BE OIOOOOOO 00BF OOIIIIII 00C0 OOIIIIIO 00C1 OOIIIIOI 00C2 OOIIIIOO 00C3 OOIIIOII 00C4 OOIIIOIO 00C5 OOIIIOOI 00C6 OOIIIOOO 00C7 OOIIOIII 00C8 OOIIOIIO 00C9 OOIIOIOI 00CA OOIIOIOO 00CB OOIIOOII 00CC OOIIOOIO 00CD OOIIOOOI 00CE OOIIOOOO 00CF OOIOIIII 00D0 OOIOIIIO 00D1 OOIOIIOI 00D2 OOIOIIOO 00D3 OOIOIOII 00D4 OOIOIOIO 00D5 OOIOIOOI 00D6 OOIOIOOO 00D7 OOIOOIII 00D8 OOIOOIIO 00D9 OOIOOIOI 00DA OOIOOIOO 00DB OOIOOOII 00DC OOIOOOIO 00DD OOIOOOOI 00DE OOIOOOOO 00DF OOOIIIII 00E0 OOOIIIIO 00E1 OOOIIIOI 00E2 OOOIIIOO 00E3 OOOIIOII 00E4 OOOIIOIO 00E5 OOOIIOOI 00E6 OOOIIOOO 00E7 OOOIOIII 00E8 OOOIOIIO 00E9 OOOIOIOI 00EA OOOIOIOO 00EB OOOIOOII 00EC OOOIOOIO 00ED OOOIOOOI 00EE OOOIOOOO 00EF OOOOIIII 00F0 OOOOIIIO 00F1 OOOOIIOI 00F2 OOOOIIOO 00F3 OOOOIOII 00F4 OOOOIOIO 00F5 OOOOIOOI 00F6 OOOOIOOO 00F7 OOOOOIII 00F8 OOOOOIIO 00F9 OOOOOIOI 00FA OOOOOIOO 00FB OOOOOOII 00FC OOOOOOIO 00FD OOOOOOOI 00FE OOOOOOOO 00FF OPTION_LOCATION 7FFF PE 0005 PEN 0007 PGMTIM 00E1 PORTA 00A0 PORTAC 00A1 PORTAD 00A0 PORTAP 00A2 PORTB 00A4 PORTBC 00A5 PORTBD 00A4 PORTBP 00A6 PORTC 00D8 PORTCC 00D9 PORTCD 00D8 PORTCP 00DA PORTD 00DC PORTDD 00DC PORTE 0090 PORTEC 0091 PORTED 0090 PORTEP 0092 PORTF 0094 PORTFC 0095 PORTFD 0094 PORTFP 0096 PORTG 00D4 PORTGC 00D5 PORTGD 00D4 PORTGP 00D6 PORTL 00D0 PORTLC 00D1 PORTLD 00D0 PORTLP 00D2 PSC 0001 PSEL0 0005 PSEL1 0006 PSR 00BE PSW 00EF RAM_BANK0_SIZE 0028 RAM_BANK0_START 0008 RAM_BANK1_SIZE 0080 RAM_BANK1_START 0100 RAM_BANK2_SIZE 0080 RAM_BANK2_START 0200 RAM_BANK3_SIZE 0080 RAM_BANK3_START 0300 RAM_BANK4_SIZE 0080 RAM_BANK4_START 0400 RAM_BANK5_SIZE 0080 RAM_BANK5_START 0500 RAM_BANK6_SIZE 0080 RAM_BANK6_START 0600 RAM_BANK7_SIZE 0080 RAM_BANK7_START 0700 RAM_REGISTERS_SIZE 000B RAM_REGISTERS_START 00F1 RBFL 0001 RBIT9 0003 RBUF 00B9 RCVG 0000 ROM_SIZE 8000 S 00FF SEC_DISABLE 0000 SEC_ENABLE 0020 SIOR 00E9 SL0 0000 SL1 0001 SP 00FD SSEL 0004 STACK_SIZE 0040 STP2 0007 T0EN 0004 T0PND 0005 T1C0 0004 T1C1 0005 T1C2 0006 T1C3 0007 T1ENA 0004 T1ENB 0000 T1PND 0005 T1PNDA 0005 T1PNDB 0001 T1RAHI 00ED T1RALO 00EC T1RBHI 00E7 T1RBLO 00E6 T2C0 0004 T2C1 0005 T2C2 0006 T2C3 0007 T2CNTRL 00C6 T2ENA 0002 T2ENB 0000 T2HS 0000 T2PNDA 0003 T2PNDB 0001 T2RAHI 00C3 T2RALO 00C2 T2RBHI 00C5 T2RBLO 00C4 T3C0 0004 T3C1 0005 T3C2 0006 T3C3 0007 T3CNTRL 00B6 T3ENA 0002 T3ENB 0000 T3HS 0001 T3PNDA 0003 T3PNDB 0001 T3RAHI 00B3 T3RALO 00B2 T3RBHI 00B5 T3RBLO 00B4 TBMT 0000 TBUF 00B8 TINTA 00AD TINTB 00AE TMR2HI 00C1 TMR2LO 00C0 TMR3HI 00B1 TMR3LO 00B0 TMRHI 00EB TMRLO 00EA VIS_OPCODE 00B4 WDSVR 00C7 WD_DISABLE 0004 WD_ENABLE 0000 X 00FC XBIT9 0005 XMTG 0001 XRCLK 0003 XTCLK 0002 __BCdirect 0001 __EXT 01FA __MAIN 0200 __MICRO 01F2 __PORTL 01E2 __RESET 0000 __STARTUP Fun 0000 __SWI 01FE __TIMERT0 01F8 __TIMERT1A 01F6 __TIMERT1B 01F4 __TIMERT2A 01EA __TIMERT2B 01E8 __TIMERT3A 01E6 __TIMERT3B 01E4 __UARTR 01EE __UARTT 01EC __VIS 01E0 __longAC Reg 0002 __longIX Reg 0000 bank0 0001 bank1 0002 bank2 0003 bank3 0004 bank4 0005 bank5 0006 bank6 0007 bank7 0008 main Fun 0200 register 0009 uWEN 0002 uWPND 0003 REGISTER USAGE MAP ('X' = Used, '-' = Unused) 0000 : ---------------- ---------------- ---------------- XXXXXXXXXXXXXXXX 0040 : XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX ---------------- 0080 : ---------------- ---------------- ---------------- ---------------- 00C0 : ---------------- ---------------- ---------------- ---------------- 0100 : ---------------- ---------------- ---------------- ---------------- 0140 : ---------------- ---------------- ---------------- ---------------- 0180 : ---------------- ---------------- ---------------- ---------------- 01C0 : ---------------- ---------------- ---------------- ---------------- RAM USAGE MAP 0000 __longIX signed long 0002 __longAC signed long 00FE BREG unsigned char 00FC X portrw 00FD SP portrw 00FE B portrw 00FF S portrw 0090 PORTE portrw 0090 PORTED portrw 0091 PORTEC portrw 0092 PORTEP portr 0094 PORTF portrw 0094 PORTFD portrw 0095 PORTFC portrw 0096 PORTFP portr 00A0 PORTA portrw 00A0 PORTAD portrw 00A1 PORTAC portrw 00A2 PORTAP portr 00A4 PORTB portrw 00A4 PORTBD portrw 00A5 PORTBC portrw 00A6 PORTBP portr 00AD TINTA portr 00AE TINTB portr 00AF HSTCR portrw 00D0 PORTL portrw 00D0 PORTLD portrw 00D1 PORTLC portrw 00D2 PORTLP portr 00D4 PORTG portrw 00D4 PORTGD portrw 00D5 PORTGC portrw 00D6 PORTGP portr 00D8 PORTC portrw 00D8 PORTCD portrw 00D9 PORTCC portrw 00DA PORTCP portr 00DC PORTD portrw 00DC PORTDD portrw 00EE CNTRL portrw 00EF PSW portrw 00E8 ICNTRL portrw 00EA TMRLO portrw 00EB TMRHI portrw 00EC T1RALO portrw 00ED T1RAHI portrw 00E6 T1RBLO portrw 00E7 T1RBHI portrw 00C6 T2CNTRL portrw 00C0 TMR2LO portrw 00C1 TMR2HI portrw 00C2 T2RALO portrw 00C3 T2RAHI portrw 00C4 T2RBLO portrw 00C5 T2RBHI portrw 00B6 T3CNTRL portrw 00B0 TMR3LO portrw 00B1 TMR3HI portrw 00B2 T3RALO portrw 00B3 T3RAHI portrw 00B4 T3RBLO portrw 00B5 T3RBHI portrw 00E9 SIOR portrw 00CF ITMR portrw 00CB ENAD portrw 00CD ADRSLTL portrw 00CC ADRSLTH portrw 00A8 ISPAD portrw 00A8 ISPADLO portrw 00A9 ISPADHI portrw 00AA ISPRD portrw 00AB ISPWR portrw 00E1 PGMTIM portrw 00E2 ISPKEY portrw 00B8 TBUF portrw 00B9 RBUF portrw 00BA ENU portrw 00BB ENUR portrw 00BC ENUI portrw 00BD BAUD portrw 00BE PSR portrw 00C7 WDSVR portrw 00C8 LWKEDG portrw 00C9 LWKEN portrw 00CA LWKPND portrw LOCAL RAM USAGE FROM 0780 TO 077F ROM USAGE MAP 0000 to 0004 00FF to 0100 0200 to 020F Total ROM used 0017 (23) Errors : 0 Warnings : 0