COP8 "C" COMPILER V3.51 25-Mar-2002 PAGE 1 #pragma option f0 #pragma option RAMMAP /* * COP8C Code Development System * Tutorial Example * RTCCINT3.C * This code may be adapted for any purpose * when used with the COP8C Code Development * System. No warranty is implied or given * as to their usability for any purpose. * * (c) Copyright 2000 Byte Craft Limited * 421 King St.N., Waterloo, ON, Canada, N2J 4E4 * VOICE: 1 (519) 888 6911 * FAX : 1 (519) 746 6751 * email: support@bytecraft.com * * REVISION HISTORY * v1.00 AL 01/2000 Initial Version. */ #include #ifndef __COP8C_H 0007 #define __COP8C_H /* COP8C Code Development System Header file for National Semiconductor: COP640C/COP840C/COP940C COP642C/COP842C/COP942C This code may be adapted for any purpose when used with the COP8C Code Development System. No warranty is implied or given as to their usability for any purpose. (c) Copyright 1998,1999,2000 Byte Craft Limited 421 King St.N., Waterloo, ON, Canada, N2J 4E4 VOICE: 1 (519) 888 6911 FAX : 1 (519) 746 6751 email: support@bytecraft.com Michael Lee (MEKL) REVISION HISTORY V3.00 ML 05/98 Initial Version V3.01 AL 06/98 modified SaveContext and RestoreContext macros V3.02 AL 06/98 modified SaveContext and RestoreContext macros V3.03 AL 10/98 modified RAM declarations, reserved 0xF0 for compiler fixed '#pragma has' and removed Save/RestoreContext macros */ /* PRAGMA HAS */ #pragma has 840; 0008 #define __BASIC_FAMILY 00FE #pragma regb BREG; 00EF #pragma regix IX; 00EF #pragma regac AC; 00FC #pragma portrw X @ 0xFC; 00FD #pragma portrw SP @ 0xFD; 00FE #pragma portrw B @ 0xFE; /* MEMORY INFO */ 0800 #define ROM_SIZE 2048 0102 #define CODE_START 0x102 0102 06FE #pragma memory ROM [ROM_SIZE - CODE_START] @ CODE_START; 0020 #define STACK_SIZE 0x20 0008 #define RAM_BANK0_START 8 /* leave space for compiler temps 0x0-0x7 */ 0048 #define RAM_BANK0_SIZE 0x70-RAM_BANK0_START-STACK_SIZE 00F1 #define RAM_REGISTERS_START 0xF1 /* reserve 0xF0 for compiler */ 000B #define RAM_REGISTERS_SIZE 0xFC-RAM_REGISTERS_START 0050 0020 #pragma memory STACK [STACK_SIZE] @ RAM_BANK0_START+RAM_BANK0_SIZE; 0008 0048 #pragma memory RAM bank0 [RAM_BANK0_SIZE] @ RAM_BANK0_START; 004F 0000 #pragma memory LOCAL [0] @ RAM_BANK0_START+RAM_BANK0_SIZE-1; 00F1 000B #pragma memory RAM register [RAM_REGISTERS_SIZE] @ RAM_REGISTERS_START; /* PORTL */ 00D0 #pragma portrw PORTL @ 0xD0; /* PORTL data register */ 00D0 #pragma portrw PORTLD @ 0xD0; /* PORTL data register */ 00D1 #pragma portrw PORTLC @ 0xD1; /* PORTL configuration register */ 00D2 #pragma portr PORTLP @ 0xD2; /* PORTL input pins */ /* PORTG */ 00D4 #pragma portrw PORTG @ 0xD4; /* PORTG data register */ 00D4 #pragma portrw PORTGD @ 0xD4; /* PORTG data register */ 00D5 #pragma portrw PORTGC @ 0xD5; /* PORTG configuration register */ 00D6 #pragma portr PORTGP @ 0xD6; /* PORTG input pins */ /* PORTD */ 00DC #pragma portrw PORTD @ 0xDC; /* PORTD data register */ 00DC #pragma portrw PORTDD @ 0xDC; /* PORTD data register */ /* PORTI */ 00D7 #pragma portr PORTIP @ 0xD7; /* PORTI input pins */ /* control registers */ 00EE #pragma portrw CNTRL @ 0xEE; /* CNTRL control register */ 0007 #define TC1 7 /* timer T1 mode control bit */ 0007 #define T1C1 7 /* timer T1 mode control bit */ 0006 #define TC2 6 /* timer T1 mode control bit */ 0006 #define T1C2 6 /* timer T1 mode control bit */ 0005 #define TC3 5 /* timer T1 mode control bit */ 0005 #define T1C3 5 /* timer T1 mode control bit */ 0004 #define TRUN 4 /* start/stop the timer/counter */ 0003 #define MSEL 3 /* selects G5 and G4 as MICROWIRE/PLUS signals SK and SO */ 0002 #define IEDG 2 /* external interrupt edge polarity select */ 0001 #define SL1 1 /* select MICROWIRE/PLUS clock divide */ 0000 #define SL0 0 /* select MICROWIRE/PLUS clock divide */ 00EF #pragma portrw PSW @ 0xEF; /* PSW register */ 0007 #define HC 7 /* half carry flag */ 0006 #define C 6 /* carry flag */ 0005 #define T1PND 5 /* timer T1 interrupt pending flag */ 0005 #define T1PNDA 5 /* timer T1 interrupt pending flag */ 0005 #define TPND 5 /* timer T1 interrupt pending flag */ 0004 #define T1ENA 4 /* timer T1 interrupt enable for timer underflow or T1A */ 0004 #define ENTI 4 /* timer T1 interrupt enable for timer underflow or T1A */ 0003 #define EXPND 3 /* external interrupt pending */ 0003 #define IPND 3 /* external interrupt pending */ 0002 #define BUSY 2 /* MICROWIRE/PLUS busy shifting flag */ 0001 #define EXEN 1 /* enable external interrupt */ 0001 #define ENI 1 /* enable external interrupt */ 0000 #define GIE 0 /* global interrupt enable */ /* timer 1 */ 00EA #pragma portrw TMRLO @ 0xEA; /* timer T1 lower byte */ 00EB #pragma portrw TMRHI @ 0xEB; /* timer T1 upper byte */ 00EC #pragma portrw T1RALO @ 0xEC; /* timer T1 autoload register T1RA lower byte */ 00ED #pragma portrw T1RAHI @ 0xED; /* timer T1 autoload register T1RA upper byte */ 00E6 #pragma portrw T1RBLO @ 0xE6; /* timer T1 autoload register T1RB lower byte */ 00E7 #pragma portrw T1RBHI @ 0xE7; /* timer T1 autoload register T1RB upper byte */ 00E9 #pragma portrw SIOR @ 0xE9; /* MICROWIRE/PLUS shift register */ #endif /* __640C_H */ #include #ifndef __PORT_H 0009 #define __PORT_H #endif /* __PORT_H */ 000C #define __NO16BIT_NOMATH_ISR #include #ifndef __COP8_ISR_H 000D #define __COP8_ISR_H /* * COP8C Code Development System * basic interrupt library routines * COP8_ISR.C * This code may be adapted for any purpose * when used with the COP8C Code Development * System. No warranty is implied or given * as to their usability for any purpose. * * (c) Copyright 2000 Byte Craft Limited * 421 King St.N., Waterloo, ON, Canada, N2J 4E4 * VOICE: 1 (519) 888 6911 * FAX : 1 (519) 746 6751 * email: support@bytecraft.com * * REVISION HISTORY * V0.90b AL 07/00 Initial Version. */ /* This library is used to simplify the use of * interrupts within C on all "COP8 BASIC FAMILY" * processors (processors without PUSH/POP instrustions * and no interrupt vector table) */ /* * possible conditions: * __BASIC_FAMILY * __NOLONG_MATH_ISR * __SREG */ #ifdef __BASIC_FAMILY 00FF #pragma vector __INT @ 0x00FF; /* use SaveContext and RestoreContext macros to save COP8 registers in the interrupt subroutines */ #ifdef __NO16BIT_NOMATH_ISR 0008 0005 unsigned char temp_CONTEXT[5]; #asm MACRO __SAVE_16BIT_MATH ENDM MACRO __RESTORE_16BIT_MATH LD B,#(temp_CONTEXT+4) ENDM #endasm #else unsigned char temp_CONTEXT[13]; #asm expand MACRO __SAVE_16BIT_MATH LD B,#0 ;B points to MATH/16bit temps \_dec_next_context_save: LD A,[B+] ;save 0x00 - 0x07 to temp_CONTEXT[5-12] X A,[X+] IFBNE #8 JP \_dec_next_context_save ENDM MACRO __RESTORE_16BIT_MATH LD X,#(temp_CONTEXT+12) LD B,#7 ;B points to MATH/16bit temps \_dec_next_context_restore: LD A,[X-] ;save 0x00 - 0x07 to temp_CONTEXT[5-12] X A,[B-] IFBNE #0 JP \_dec_next_context_restore ENDM #endasm #endif /* __NO16BIT_NOMATH_ISR */ #asm MACRO ASM_SAVE_CONTEXT X A,temp_CONTEXT ;store temp_CONTEXT[0] = AREG LD A,X ;save X in A LD X,#temp_CONTEXT+1 ;load X with &temp_CONTEXT X A,[X+] ;store temp_CONTEXT[1] = X LD A,B X A,[X+] ;store temp_CONTEXT[2] = B LD A,PSW X A,[X+] ;store temp_CONTEXT[3] = PSW LD A,0xf0 X A,[X+] ;store temp_CONTEXT[4] = compiler temp __SAVE_16BIT_MATH ENDM MACRO ASM_RESTORE_CONTEXT __RESTORE_16BIT_MATH LD A,[B-] X A,0xf0 ;restore compiler temp LD A,[B] ADD A,[B] ;bit 7 into carry RBIT #7,$EF IFC SBIT #7,$EF ;set half carry RBIT #6,$EF IFBIT #6,[B] SC DRSZ B LD A,[B-] ;resotre B X A,B LD A,temp_CONTEXT+1 ;resotre X X A,X LD A,temp_CONTEXT ;resotre A ENDM #endasm #else /* __BASIC_FAMILY */ #ifdef __SREG #asm MACRO __SAVE_SREG LD A,S PUSH A ENDM MACRO __RESTORE_SREG POP A X A,S ENDM MACRO __CLEAR_SREG LD S,#0 ENDM #endasm #else /* __SREG */ #asm MACRO __RESTORE_SREG ENDM MACRO __SAVE_SREG ENDM MACRO __CLEAR_SREG ENDM #endasm #endif /* __SREG */ #ifdef __NO16BIT_NOMATH_ISR #asm MACRO __SAVE_16BIT_MATH ENDM MACRO __RESTORE_16BIT_MATH ENDM #endasm #else #asm MACRO __SAVE_16BIT_MATH __CLEAR_SREG LD B,#0 \_dec_next_context_save: LD A,[B+] ;save 0x00 - 0x07 on stack PUSH A IFBNE #8 JP \_dec_next_context_save ENDM MACRO __RESTORE_16BIT_MATH __CLEAR_SREG LD B,#7 ;B points to MATH/16bit temps \_dec_next_context_restore: POP A X A,[B-] ;restore 0x00 - 0x07 from stack IFBNE #0 JP \_dec_next_context_restore POP A X A,[B] ENDM #endasm #endif /* __NO16BIT_NOMATH_ISR */ #asm MACRO ASM_SAVE_CONTEXT PUSH A LD A,B PUSH A LD A,PSW PUSH A LD A,$F0 ;save compiler temp PUSH A __SAVE_SREG LD A,X PUSH A __SAVE_16BIT_MATH ENDM MACRO ASM_RESTORE_CONTEXT __RESTORE_16BIT_MATH POP A X A,X __RESTORE_SREG POP A X A,$F0 ;restore compiler temp POP A RC LD B,#PSW ;restore only C and HC from PSW IFBIT 7,A SBIT 7,[B] IFBIT 6,A SBIT 6,[B] POP A X A,B POP A ENDM #endasm #endif /* __BASIC_FAMILY */ /* use SaveContext and RestoreContext macros to save COP8 registers in the * interrupt subroutines */ 000E #define SaveContext() #asm( ASM_SAVE_CONTEXT) 000F #define RestoreContext() #asm( ASM_RESTORE_CONTEXT) #endif /* __COP8_ISR_H */ 000D unsigned int rtcc_total; void __INT(void) { SaveContext(); 0102 9C 08 X A,008 0104 9D FC LD A,X 0106 DC 09 LD X,#009 0108 B2 X A,[X+] 0109 9D FE LD A,B 010B B2 X A,[X+] 010C 9D EF LD A,0EF 010E B2 X A,[X+] 010F 9D F0 LD A,0F0 0111 B2 X A,[X+] 000E unsigned int interrupt_temp; 0112 51 LD B,#0E 0113 AE LD A,[B] 0114 9C FC X A,X 0116 9D FC LD A,X 0118 92 00 IFEQ A,#000 rtcc_total <<= interrupt_temp; 011A 09 JP 00124 011B 9D 0D LD A,00D 011D BD 0D 84 ADD A,00D 0120 52 LD B,#0D 0121 A6 X A,[B] 0122 CC DRSZ X 0123 F7 JP 0011B 0124 51 LD B,#0E interrupt_temp++; 0125 A6 X A,[B] 0126 8A INCA 0127 A6 X A,[B] RestoreContext(); 0128 53 LD B,#0C 0129 AB LD A,[B-] 012A 9C F0 X A,0F0 012C AE LD A,[B] 012D 84 ADD A,[B] 012E BD EF 6F RBIT 07,0EF 0131 88 IFC 0132 BD EF 7F SBIT 07,0EF 0135 BD EF 6E RBIT 06,0EF 0138 76 IFBIT 06,[B] 0139 A1 SC 013A CE DRSZ B 013B AB LD A,[B-] 013C 9C FE X A,B 013E 9D 09 LD A,009 0140 9C FC X A,X 0142 9D 08 LD A,008 0144 8F RETI } 000F unsigned int main_loop_total; void main(void) { 004F unsigned int count; DDR(PORTL,IIIIOIII); /* set PORTL.3 as output */ while(1) 0145 BC D1 08 LD 0D1,#08 0148 9D 4F LD A,04F 014A 94 80 ADD A,#080 { 014C 50 LD B,#0F main_loop_total += count - 0x80; 014D 84 ADD A,[B] 014E A6 X A,[B] 014F DE 4F LD B,#04F count++; 0151 A6 X A,[B] 0152 8A INCA 0153 A6 X A,[B] 0154 F3 JP 00148 } } #ifndef __COP8_ISR_C 0010 #define __COP8_ISR_C /* * COP8C Code Development System * basic interrupt library routines * COP8_ISR.C * This code may be adapted for any purpose * when used with the COP8C Code Development * System. No warranty is implied or given * as to their usability for any purpose. * * (c) Copyright 2000 Byte Craft Limited * 421 King St.N., Waterloo, ON, Canada, N2J 4E4 * VOICE: 1 (519) 888 6911 * FAX : 1 (519) 746 6751 * email: support@bytecraft.com * * REVISION HISTORY * V0.90b AL 07/00 Initial Version. */ /* These pragma directives put a 'JMPL __INT' at the * interrup vector (0x00FF) if the function __INT is * defined*/ #ifdef __BASIC_FAMILY #ifdef __INT #if __INT != 0xff 00FF AD #pragma ECON @ 0xff = 0xAD; 0100 01 #pragma ECON @ 0x100 = __INT>>8; 0101 02 #pragma ECON @ 0x101 = __INT; #endif #endif /* __INT */ #endif /* __BASIC_FAMILY */ #endif /* __COP8_ISR_C */ #endif /* __COP8C_C */ 0000 DD 6F LD SP,#06F 0002 AC 01 55 JMPL 00155 __MAIN: 0155 AC 01 45 JMPL 00145 SYMBOL TABLE LABEL VALUE LABEL VALUE B 00FE BREG Reg 00FE BUSY 0002 C 0006 CNTRL 00EE CODE_START 0102 ENI 0001 ENTI 0004 EXEN 0001 EXPND 0003 GIE 0000 HC 0007 IEDG 0002 IIIIIIII 0000 IIIIIIIO 0001 IIIIIIOI 0002 IIIIIIOO 0003 IIIIIOII 0004 IIIIIOIO 0005 IIIIIOOI 0006 IIIIIOOO 0007 IIIIOIII 0008 IIIIOIIO 0009 IIIIOIOI 000A IIIIOIOO 000B IIIIOOII 000C IIIIOOIO 000D IIIIOOOI 000E IIIIOOOO 000F IIIOIIII 0010 IIIOIIIO 0011 IIIOIIOI 0012 IIIOIIOO 0013 IIIOIOII 0014 IIIOIOIO 0015 IIIOIOOI 0016 IIIOIOOO 0017 IIIOOIII 0018 IIIOOIIO 0019 IIIOOIOI 001A IIIOOIOO 001B IIIOOOII 001C IIIOOOIO 001D IIIOOOOI 001E IIIOOOOO 001F IIOIIIII 0020 IIOIIIIO 0021 IIOIIIOI 0022 IIOIIIOO 0023 IIOIIOII 0024 IIOIIOIO 0025 IIOIIOOI 0026 IIOIIOOO 0027 IIOIOIII 0028 IIOIOIIO 0029 IIOIOIOI 002A IIOIOIOO 002B IIOIOOII 002C IIOIOOIO 002D IIOIOOOI 002E IIOIOOOO 002F IIOOIIII 0030 IIOOIIIO 0031 IIOOIIOI 0032 IIOOIIOO 0033 IIOOIOII 0034 IIOOIOIO 0035 IIOOIOOI 0036 IIOOIOOO 0037 IIOOOIII 0038 IIOOOIIO 0039 IIOOOIOI 003A IIOOOIOO 003B IIOOOOII 003C IIOOOOIO 003D IIOOOOOI 003E IIOOOOOO 003F IOIIIIII 0040 IOIIIIIO 0041 IOIIIIOI 0042 IOIIIIOO 0043 IOIIIOII 0044 IOIIIOIO 0045 IOIIIOOI 0046 IOIIIOOO 0047 IOIIOIII 0048 IOIIOIIO 0049 IOIIOIOI 004A IOIIOIOO 004B IOIIOOII 004C IOIIOOIO 004D IOIIOOOI 004E IOIIOOOO 004F IOIOIIII 0050 IOIOIIIO 0051 IOIOIIOI 0052 IOIOIIOO 0053 IOIOIOII 0054 IOIOIOIO 0055 IOIOIOOI 0056 IOIOIOOO 0057 IOIOOIII 0058 IOIOOIIO 0059 IOIOOIOI 005A IOIOOIOO 005B IOIOOOII 005C IOIOOOIO 005D IOIOOOOI 005E IOIOOOOO 005F IOOIIIII 0060 IOOIIIIO 0061 IOOIIIOI 0062 IOOIIIOO 0063 IOOIIOII 0064 IOOIIOIO 0065 IOOIIOOI 0066 IOOIIOOO 0067 IOOIOIII 0068 IOOIOIIO 0069 IOOIOIOI 006A IOOIOIOO 006B IOOIOOII 006C IOOIOOIO 006D IOOIOOOI 006E IOOIOOOO 006F IOOOIIII 0070 IOOOIIIO 0071 IOOOIIOI 0072 IOOOIIOO 0073 IOOOIOII 0074 IOOOIOIO 0075 IOOOIOOI 0076 IOOOIOOO 0077 IOOOOIII 0078 IOOOOIIO 0079 IOOOOIOI 007A IOOOOIOO 007B IOOOOOII 007C IOOOOOIO 007D IOOOOOOI 007E IOOOOOOO 007F IPND 0003 MSEL 0003 OIIIIIII 0080 OIIIIIIO 0081 OIIIIIOI 0082 OIIIIIOO 0083 OIIIIOII 0084 OIIIIOIO 0085 OIIIIOOI 0086 OIIIIOOO 0087 OIIIOIII 0088 OIIIOIIO 0089 OIIIOIOI 008A OIIIOIOO 008B OIIIOOII 008C OIIIOOIO 008D OIIIOOOI 008E OIIIOOOO 008F OIIOIIII 0090 OIIOIIIO 0091 OIIOIIOI 0092 OIIOIIOO 0093 OIIOIOII 0094 OIIOIOIO 0095 OIIOIOOI 0096 OIIOIOOO 0097 OIIOOIII 0098 OIIOOIIO 0099 OIIOOIOI 009A OIIOOIOO 009B OIIOOOII 009C OIIOOOIO 009D OIIOOOOI 009E OIIOOOOO 009F OIOIIIII 00A0 OIOIIIIO 00A1 OIOIIIOI 00A2 OIOIIIOO 00A3 OIOIIOII 00A4 OIOIIOIO 00A5 OIOIIOOI 00A6 OIOIIOOO 00A7 OIOIOIII 00A8 OIOIOIIO 00A9 OIOIOIOI 00AA OIOIOIOO 00AB OIOIOOII 00AC OIOIOOIO 00AD OIOIOOOI 00AE OIOIOOOO 00AF OIOOIIII 00B0 OIOOIIIO 00B1 OIOOIIOI 00B2 OIOOIIOO 00B3 OIOOIOII 00B4 OIOOIOIO 00B5 OIOOIOOI 00B6 OIOOIOOO 00B7 OIOOOIII 00B8 OIOOOIIO 00B9 OIOOOIOI 00BA OIOOOIOO 00BB OIOOOOII 00BC OIOOOOIO 00BD OIOOOOOI 00BE OIOOOOOO 00BF OOIIIIII 00C0 OOIIIIIO 00C1 OOIIIIOI 00C2 OOIIIIOO 00C3 OOIIIOII 00C4 OOIIIOIO 00C5 OOIIIOOI 00C6 OOIIIOOO 00C7 OOIIOIII 00C8 OOIIOIIO 00C9 OOIIOIOI 00CA OOIIOIOO 00CB OOIIOOII 00CC OOIIOOIO 00CD OOIIOOOI 00CE OOIIOOOO 00CF OOIOIIII 00D0 OOIOIIIO 00D1 OOIOIIOI 00D2 OOIOIIOO 00D3 OOIOIOII 00D4 OOIOIOIO 00D5 OOIOIOOI 00D6 OOIOIOOO 00D7 OOIOOIII 00D8 OOIOOIIO 00D9 OOIOOIOI 00DA OOIOOIOO 00DB OOIOOOII 00DC OOIOOOIO 00DD OOIOOOOI 00DE OOIOOOOO 00DF OOOIIIII 00E0 OOOIIIIO 00E1 OOOIIIOI 00E2 OOOIIIOO 00E3 OOOIIOII 00E4 OOOIIOIO 00E5 OOOIIOOI 00E6 OOOIIOOO 00E7 OOOIOIII 00E8 OOOIOIIO 00E9 OOOIOIOI 00EA OOOIOIOO 00EB OOOIOOII 00EC OOOIOOIO 00ED OOOIOOOI 00EE OOOIOOOO 00EF OOOOIIII 00F0 OOOOIIIO 00F1 OOOOIIOI 00F2 OOOOIIOO 00F3 OOOOIOII 00F4 OOOOIOIO 00F5 OOOOIOOI 00F6 OOOOIOOO 00F7 OOOOOIII 00F8 OOOOOIIO 00F9 OOOOOIOI 00FA OOOOOIOO 00FB OOOOOOII 00FC OOOOOOIO 00FD OOOOOOOI 00FE OOOOOOOO 00FF PORTD 00DC PORTDD 00DC PORTG 00D4 PORTGC 00D5 PORTGD 00D4 PORTGP 00D6 PORTIP 00D7 PORTL 00D0 PORTLC 00D1 PORTLD 00D0 PORTLP 00D2 PSW 00EF RAM_BANK0_SIZE 0048 RAM_BANK0_START 0008 RAM_REGISTERS_SIZE 000B RAM_REGISTERS_START 00F1 ROM_SIZE 0800 SIOR 00E9 SL0 0000 SL1 0001 SP 00FD STACK_SIZE 0020 T1C1 0007 T1C2 0006 T1C3 0005 T1ENA 0004 T1PND 0005 T1PNDA 0005 T1RAHI 00ED T1RALO 00EC T1RBHI 00E7 T1RBLO 00E6 TC1 0007 TC2 0006 TC3 0005 TMRHI 00EB TMRLO 00EA TPND 0005 TRUN 0004 X 00FC __BCdirect 0001 __ECON 0101 __INT Fun 0102 __MAIN 0155 __RESET 0000 __STARTUP Fun 0000 __longAC Reg 0002 __longIX Reg 0000 bank0 0001 main Fun 0145 main_loop_total Reg 000F register 0002 rtcc_total Reg 000D temp_CONTEXT 0008 REGISTER USAGE MAP ('X' = Used, '-' = Unused) 0000 : --------XXXXXXXX ---------------- ---------------- ---------------- 0040 : ---------------- XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX ---------------- 0080 : ---------------- ---------------- ---------------- ---------------- 00C0 : ---------------- ---------------- ---------------- ---------------- 0100 : ---------------- ---------------- ---------------- ---------------- 0140 : ---------------- ---------------- ---------------- ---------------- 0180 : ---------------- ---------------- ---------------- ---------------- 01C0 : ---------------- ---------------- ---------------- ---------------- RAM USAGE MAP 0000 __longIX signed long 0002 __longAC signed long 00FE BREG unsigned char 00FC X portrw 00FD SP portrw 00FE B portrw 00D0 PORTL portrw 00D0 PORTLD portrw 00D1 PORTLC portrw 00D2 PORTLP portr 00D4 PORTG portrw 00D4 PORTGD portrw 00D5 PORTGC portrw 00D6 PORTGP portr 00DC PORTD portrw 00DC PORTDD portrw 00D7 PORTIP portr 00EE CNTRL portrw 00EF PSW portrw 00EA TMRLO portrw 00EB TMRHI portrw 00EC T1RALO portrw 00ED T1RAHI portrw 00E6 T1RBLO portrw 00E7 T1RBHI portrw 00E9 SIOR portrw 0008 temp_CONTEXT unsigned char[5] 000D rtcc_total unsigned char 000E interrupt_temp unsigned char 0102 0143 000F main_loop_total unsigned char 004F count unsigned char 0145 0154 00FF __ECON portrw LOCAL RAM USAGE FROM 0050 TO 004F ROM USAGE MAP 0000 to 0004 00FF to 0157 Total ROM used 005E (94) Errors : 0 Warnings : 0