COP8 "C" COMPILER V3.51 25-Mar-2002 PAGE 1 #pragma option f0 /* remove page breaks from listing file */ /* * COP8C Code Development System * Tutorial Example * VAR3.C * This code may be adapted for any purpose * when used with the COP8C Code Development * System. No warranty is implied or given * as to their usability for any purpose. * * (c) Copyright 2000 Byte Craft Limited * 421 King St.N., Waterloo, ON, Canada, N2J 4E4 * VOICE: 1 (519) 888 6911 * FAX : 1 (519) 746 6751 * email: support@bytecraft.com * * REVISION HISTORY * v1.00 AL 01/2000 Initial Version. */ #include #ifndef __COP8C_H 0007 #define __COP8C_H /* COP8C Code Development System Header file for National Semiconductor: COP8CBR This code may be adapted for any purpose when used with the COP8C Code Development System. No warranty is implied or given as to their usability for any purpose. (c) Copyright 2000 Byte Craft Limited 421 King St.N., Waterloo, ON, Canada, N2J 4E4 VOICE: 1 (519) 888 6911 FAX : 1 (519) 746 6751 email: support@bytecraft.com REVISION HISTORY V1.00 AL 01/00 Initial version */ /* PRAGMA HAS */ #pragma has 888; #pragma has SREG; 00FE #pragma regb BREG; 00EF #pragma regix IX; 00EF #pragma regac AC; 00FC #pragma portrw X @ 0xFC; 00FD #pragma portrw SP @ 0xFD; 00FE #pragma portrw B @ 0xFE; 00FF #pragma portrw S @ 0xFF; /* MEMORY INFO */ 8000 #define ROM_SIZE 32768 0200 #define CODE_START 0x200 0200 7DFF #pragma memory ROM [ROM_SIZE - CODE_START -1] @ CODE_START; 0040 #define STACK_SIZE 0x40 0008 #define RAM_BANK0_START 8 /* leave space for compiler temps 0x0-0x7 */ 0028 #define RAM_BANK0_SIZE 0x70-RAM_BANK0_START-STACK_SIZE 0100 #define RAM_BANK1_START 0x100 0200 #define RAM_BANK2_START 0x200 0300 #define RAM_BANK3_START 0x300 0400 #define RAM_BANK4_START 0x400 0500 #define RAM_BANK5_START 0x500 0600 #define RAM_BANK6_START 0x600 0700 #define RAM_BANK7_START 0x700 0080 #define RAM_BANK1_SIZE 0x80 0080 #define RAM_BANK2_SIZE 0x80 0080 #define RAM_BANK3_SIZE 0x80 0080 #define RAM_BANK4_SIZE 0x80 0080 #define RAM_BANK5_SIZE 0x80 0080 #define RAM_BANK6_SIZE 0x80 0080 #define RAM_BANK7_SIZE 0x80 00F1 #define RAM_REGISTERS_START 0xF1 /* reserve 0xF0 for compiler */ 000B #define RAM_REGISTERS_SIZE 0xFC-RAM_REGISTERS_START 0030 0040 #pragma memory STACK [STACK_SIZE] @ RAM_BANK0_START+RAM_BANK0_SIZE; 0008 0028 #pragma memory RAM bank0 [RAM_BANK0_SIZE] @ RAM_BANK0_START; 0100 0080 #pragma memory RAM bank1 [RAM_BANK1_SIZE] @ RAM_BANK1_START; 0200 0080 #pragma memory RAM bank2 [RAM_BANK2_SIZE] @ RAM_BANK2_START; 0300 0080 #pragma memory RAM bank3 [RAM_BANK3_SIZE] @ RAM_BANK3_START; 0400 0080 #pragma memory RAM bank4 [RAM_BANK4_SIZE] @ RAM_BANK4_START; 0500 0080 #pragma memory RAM bank5 [RAM_BANK5_SIZE] @ RAM_BANK5_START; 0600 0080 #pragma memory RAM bank6 [RAM_BANK6_SIZE] @ RAM_BANK6_START; 0700 0080 #pragma memory RAM bank7 [RAM_BANK7_SIZE] @ RAM_BANK7_START; 077F 0000 #pragma memory LOCAL [0] @ RAM_BANK7_START+RAM_BANK7_SIZE-1; 00F1 000B #pragma memory RAM register [RAM_REGISTERS_SIZE] @ RAM_REGISTERS_START; /* Interrupts */ 01FE #pragma vector __SWI @ 0x1FE; /* Software INTR Instruction */ 01FA #pragma vector __EXT @ 0x1FA; /* External Pin G0 edge */ 01F8 #pragma vector __TIMERT0 @ 0x1F8; /* Timer T0 Underflow */ 01F6 #pragma vector __TIMERT1A @ 0x1F6; /* Timer T1 T1A/Underflow */ 01F4 #pragma vector __TIMERT1B @ 0x1F4; /* Timer T1 T1B */ 01F2 #pragma vector __MICRO @ 0x1F2; /* MICROWIRE/PLUS */ 01EE #pragma vector __UARTR @ 0x1EE; /* UART Recieve */ 01EC #pragma vector __UARTT @ 0x1EC; /* UART Transmit */ 01EA #pragma vector __TIMERT2A @ 0x1EA; /* Timer T2 T2A/Underflow */ 01E8 #pragma vector __TIMERT2B @ 0x1E8; /* Timer T2 T2B */ 01E6 #pragma vector __TIMERT3A @ 0x1E6; /* Timer T3 T3A/Underflow */ 01E4 #pragma vector __TIMERT3B @ 0x1E4; /* Timer T3 T3B */ 01E2 #pragma vector __PORTL @ 0x1E2; /* PortL/wakeup PortL Edge */ 01E0 #pragma vector __VIS @ 0x1E0; /* Default */ /* place the VIS instruction at 0xff */ 00B4 #define VIS_OPCODE 0xb4 00FF #pragma vector INTERRUPT_BRANCH_VECTOR @ 0xFF; 00FF 02 00 void INTERRUPT_BRANCH_VECTOR(void) @ VIS_OPCODE<<8; 00FF B4 00 /* option register bit definitions */ /* #define OPTION_VAL ENABLE_SECURITY | DISABLE_WATCHDOG */ 7FFF #define OPTION_LOCATION 0x7fff 0020 #define SEC_ENABLE 0b00100000 0000 #define SEC_DISABLE 0b00000000 0004 #define WD_DISABLE 0b00000100 0000 #define WD_ENABLE 0b00000000 0002 #define HALT_DISABLE 0b00000010 0000 #define HALT_ENABLE 0b00000000 0001 #define FLEX_FLASH 0b00000001 0000 #define FLEX_ROM 0b00000000 #ifdef OPTION_VAL /*#define OPTION_VAL SEC_DISABLE | WD_ENABLE | HALT_DISABLE | FLEX_FLASH */ #pragma ECON @ OPTION_LOCATION = OPTION_VAL; #endif /* ECON_VAL */ /* PORTE */ 0090 #pragma portrw PORTE @ 0x90; /* PORTE data register */ 0090 #pragma portrw PORTED @ 0x90; /* PORTE data register */ 0091 #pragma portrw PORTEC @ 0x91; /* PORTE configuration register */ 0092 #pragma portr PORTEP @ 0x92; /* PORTE input pins */ /* PORTF */ 0094 #pragma portrw PORTF @ 0x94; /* PORTF data register */ 0094 #pragma portrw PORTFD @ 0x94; /* PORTF data register */ 0095 #pragma portrw PORTFC @ 0x95; /* PORTF configuration register */ 0096 #pragma portr PORTFP @ 0x96; /* PORTF input pins */ /* PORTA */ 00A0 #pragma portrw PORTA @ 0xA0; /* PORTA data register */ 00A0 #pragma portrw PORTAD @ 0xA0; /* PORTA data register */ 00A1 #pragma portrw PORTAC @ 0xA1; /* PORTA configuration register */ 00A2 #pragma portr PORTAP @ 0xA2; /* PORTA input pins */ /* PORTB */ 00A4 #pragma portrw PORTB @ 0xA4; /* PORTB data register */ 00A4 #pragma portrw PORTBD @ 0xA4; /* PORTB data register */ 00A5 #pragma portrw PORTBC @ 0xA5; /* PORTB configuration register */ 00A6 #pragma portr PORTBP @ 0xA6; /* PORTB input pins */ /* HSTCR */ 00AD #pragma portr TINTA @ 0xAD; /* high speed interrupt A */ 00AE #pragma portr TINTB @ 0xAE; /* high speed interrupt b */ 00AF #pragma portrw HSTCR @ 0xAF; /* high speed timer control register */ 0001 #define T3HS 1 0000 #define T2HS 0 /* PORTL */ 00D0 #pragma portrw PORTL @ 0xD0; /* PORTL data register */ 00D0 #pragma portrw PORTLD @ 0xD0; /* PORTL data register */ 00D1 #pragma portrw PORTLC @ 0xD1; /* PORTL configuration register */ 00D2 #pragma portr PORTLP @ 0xD2; /* PORTL input pins */ /* PORTG */ 00D4 #pragma portrw PORTG @ 0xD4; /* PORTG data register */ 00D4 #pragma portrw PORTGD @ 0xD4; /* PORTG data register */ 00D5 #pragma portrw PORTGC @ 0xD5; /* PORTG configuration register */ 00D6 #pragma portr PORTGP @ 0xD6; /* PORTG input pins */ /* PORTC */ 00D8 #pragma portrw PORTC @ 0xD8; /* PORTC data register */ 00D8 #pragma portrw PORTCD @ 0xD8; /* PORTC data register */ 00D9 #pragma portrw PORTCC @ 0xD9; /* PORTC configuration register */ 00DA #pragma portr PORTCP @ 0xDA; /* PORTC input pins */ /* PORTD */ 00DC #pragma portrw PORTD @ 0xDC; /* PORTD data register */ 00DC #pragma portrw PORTDD @ 0xDC; /* PORTD data register */ /* control registers */ 00EE #pragma portrw CNTRL @ 0xEE; /* CNTRL control register */ 0007 #define T1C3 7 /* timer T1 mode control bit */ 0006 #define T1C2 6 /* timer T1 mode control bit */ 0005 #define T1C1 5 /* timer T1 mode control bit */ 0004 #define T1C0 4 /* timer T1 mode control bit */ 0003 #define MSEL 3 /* selects G5 and G4 as MICROWIRE/PLUS signals SK and SO */ 0002 #define IEDG 2 /* external interrupt edge polarity select */ 0001 #define SL1 1 /* select MICROWIRE/PLUS clock divide */ 0000 #define SL0 0 /* select MICROWIRE/PLUS clock divide */ 00EF #pragma portrw PSW @ 0xEF; /* PSW register */ 0007 #define HC 7 /* half carry flag */ 0006 #define C 6 /* carry flag */ 0005 #define T1PND 5 /* timer T1 interrupt pending flag */ 0005 #define T1PNDA 5 /* timer T1 interrupt pending flag */ 0004 #define T1ENA 4 /* timer T1 interrupt enable for timer underflow or T1A */ 0003 #define EXPND 3 /* external interrupt pending */ 0002 #define BUSY 2 /* MICROWIRE/PLUS busy shifting flag */ 0001 #define EXEN 1 /* enable external interrupt */ 0000 #define GIE 0 /* global interrupt enable */ 00E8 #pragma portrw ICNTRL @ 0xE8; /* ICNTRL register */ 0006 #define LPEN 6 /* PORTL interrupt enable */ 0005 #define T0PND 5 /* timer T0 interrupt pending */ 0004 #define T0EN 4 /* timer T0 interrupt enable */ 0003 #define uWPND 3 /* MICROWIRE/PLUS interrupt pending */ 0002 #define uWEN 2 /* enable MICROWIRE/PLUS interrupt */ 0001 #define T1PNDB 1 /* timer T1 interrupt pending flag for T1B capture edge */ 0000 #define T1ENB 0 /* timer T1 interrupt enable for T1B input capture edge */ /* timer 1 */ 00EA #pragma portrw TMRLO @ 0xEA; /* timer T1 lower byte */ 00EB #pragma portrw TMRHI @ 0xEB; /* timer T1 upper byte */ 00EC #pragma portrw T1RALO @ 0xEC; /* timer T1 autoload register T1RA lower byte */ 00ED #pragma portrw T1RAHI @ 0xED; /* timer T1 autoload register T1RA upper byte */ 00E6 #pragma portrw T1RBLO @ 0xE6; /* timer T1 autoload register T1RB lower byte */ 00E7 #pragma portrw T1RBHI @ 0xE7; /* timer T1 autoload register T1RB upper byte */ /* timer 2 */ 00C6 #pragma portrw T2CNTRL @ 0xC6; /* timer T2 control register */ 0007 #define T2C3 7 /* timer T2 mode control bit */ 0006 #define T2C2 6 /* timer T2 mode control bit */ 0005 #define T2C1 5 /* timer T2 mode control bit */ 0004 #define T2C0 4 /* timer T2 mode control bit */ 0003 #define T2PNDA 3 /* timer T2 interrupt pending flag */ 0002 #define T2ENA 2 /* timer T2 interrupt enable for timer underflow or T2A */ 0001 #define T2PNDB 1 /* timer T2 interrupt pending flag */ 0000 #define T2ENB 0 /* timer T2 interrupt enable for T2B input capture edge */ 00C0 #pragma portrw TMR2LO @ 0xC0; /* timer T2 lower byte */ 00C1 #pragma portrw TMR2HI @ 0xC1; /* timer T2 upper byte */ 00C2 #pragma portrw T2RALO @ 0xC2; /* timer T2 autoload register T2RA lower byte */ 00C3 #pragma portrw T2RAHI @ 0xC3; /* timer T2 autoload register T2RA upper byte */ 00C4 #pragma portrw T2RBLO @ 0xC4; /* timer T2 autoload register T2RB lower byte */ 00C5 #pragma portrw T2RBHI @ 0xC5; /* timer T2 autoload register T2RB upper byte */ /* timer 3 */ 00B6 #pragma portrw T3CNTRL @ 0xB6; /* timer T3 control register */ 0007 #define T3C3 7 /* timer T3 mode control bit */ 0006 #define T3C2 6 /* timer T3 mode control bit */ 0005 #define T3C1 5 /* timer T3 mode control bit */ 0004 #define T3C0 4 /* timer T3 mode control bit */ 0003 #define T3PNDA 3 /* timer T3 interrupt pending flag */ 0002 #define T3ENA 2 /* timer T3 interrupt enable for timer underflow or T3A */ 0001 #define T3PNDB 1 /* timer T3 interrupt pending flag */ 0000 #define T3ENB 0 /* timer T3 interrupt enable for T3B input capture edge */ 00B0 #pragma portrw TMR3LO @ 0xB0; /* timer T3 lower byte */ 00B1 #pragma portrw TMR3HI @ 0xB1; /* timer T3 upper byte */ 00B2 #pragma portrw T3RALO @ 0xB2; /* timer T3 autoload register T3RA lower byte */ 00B3 #pragma portrw T3RAHI @ 0xB3; /* timer T3 autoload register T3RA upper byte */ 00B4 #pragma portrw T3RBLO @ 0xB4; /* timer T3 autoload register T3RB lower byte */ 00B5 #pragma portrw T3RBHI @ 0xB5; /* timer T3 autoload register T3RB upper byte */ 00E9 #pragma portrw SIOR @ 0xE9; /* MICROWIRE/PLUS shift register */ /* ITMR */ 00CF #pragma portrw ITMR @ 0xCF; /* idle timer control register */ 0007 #define LSON 7 /* turns the low speed oscillator on or off */ 0006 #define HSON 6 /* turns the high speed oscillator on or off */ 0005 #define DCEN 5 /* clock idle timer with high speed clock */ 0004 #define CCKSEL 4 /* high speed timer as CPU clock */ 0002 #define ITSEL2 2 /* idle timer period bit */ 0001 #define ITSEL1 1 /* idle timer period bit */ 0000 #define ITSEL0 0 /* idle timer period bit */ /* ENAD */ 00CB #pragma portrw ENAD @ 0xCB; /* A/D converter control register */ 0007 #define ADCH3 7 /* ADC channel select bit */ 0006 #define ADCH2 6 /* ADC channel select bit */ 0005 #define ADCH1 5 /* ADC channel select bit */ 0004 #define ADCH0 4 /* ADC channel select bit */ 0003 #define ADMOD 3 /* places the ADC in single-ended or differential mode */ 0002 #define MUX 2 /* enables the ADC multiplexor output */ 0001 #define PSC 1 /* MCLK divide by 1 or 12 */ 0000 #define ADBSY 0 /* ADC busy (currently converting) */ /* ADRSLTL */ 00CD #pragma portrw ADRSLTL @ 0xCD; /* A/D converter result low */ /* ADRSLTH */ 00CC #pragma portrw ADRSLTH @ 0xCC; /* A/D converter result high */ /* ISPAD */ 00A8 #pragma portrw ISPAD @ 0xA8; /* ISP address register */ /* ISPADLO */ 00A8 #pragma portrw ISPADLO @ 0xA8; /* ISP address register low */ /* ISPADHI */ 00A9 #pragma portrw ISPADHI @ 0xA9; /* ISP address register high */ /* ISPRD */ 00AA #pragma portrw ISPRD @ 0xAA; /* ISP read data register low */ /* ISPWR */ 00AB #pragma portrw ISPWR @ 0xAB; /* ISP write data register low */ /* PGMTIM */ 00E1 #pragma portrw PGMTIM @ 0xE1; /* flash memory write timing register */ /* ISPKEY */ 00E2 #pragma portrw ISPKEY @ 0xE2; /* ISP key register */ /* UART */ 00B8 #pragma portrw TBUF @ 0xB8; /* UART transmit buffer */ 00B9 #pragma portrw RBUF @ 0xB9; /* UART receive buffer */ 00BA #pragma portrw ENU @ 0xBA; /* UART Control and Status */ 0007 #define PEN 7 /* enable / dis-able Parity */ 0006 #define PSEL1 6 /* Parity select bits */ 0005 #define XBIT9 5 /* Program Bit transmission or Selects Parity */ 0005 #define PSEL0 5 /* Program Bit transmission or Selects Parity */ 0004 #define CHL1 4 /* frame format selection */ 0003 #define CHL0 3 /* frame format selection */ 0002 #define ERR 2 /* error Flag */ 0001 #define RBFL 1 /* Byte Received Flag */ 0000 #define TBMT 0 /* Byte Transfered Flag */ 00BB #pragma portrw ENUR @ 0xBB; /* UART Receive Control and Status */ 0007 #define DOE 7 /* Data Overrun error */ 0006 #define FE 6 /* Flag Framing error */ 0005 #define PE 5 /* Parity error */ 0004 #define BD 4 /* flags a line break */ 0003 #define RBIT9 3 /* Ninth bit in UART nine bit mode */ 0002 #define ATTN 2 /* Attention mode enable */ 0001 #define XMTG 1 /* UART transmitting indicator */ 0000 #define RCVG 0 /* Framing error (goes low when RDX goes high) */ 00BC #pragma portrw ENUI @ 0xBC; /* UART register - Interrupt and Clock Source */ 0007 #define STP2 7 /* Sets number of Stop bits to be Transmitted */ 0006 #define BRK 6 /* Holds TDX low to generate a line break */ 0005 #define ETDX 5 /* ETDX - UART Transmit Pin */ 0004 #define SSEL 4 /* UART Mode Select */ 0003 #define XRCLK 3 /* Clock source selection reception */ 0002 #define XTCLK 2 /* Clock source selection transmission */ 0001 #define ERI 1 /* Enable / Disable Receiver interrupt */ 0000 #define ETI 0 /* Enable / Disable Transmiter Interrupt */ 00BD #pragma portrw BAUD @ 0xBD; /* UART baud register */ 00BE #pragma portrw PSR @ 0xBE; /* UART prescale select register */ 00C7 #pragma portrw WDSVR @ 0xC7; /* WATCHDOG service register */ 00C8 #pragma portrw LWKEDG @ 0xC8; /* LMIWU edge select register */ 00C9 #pragma portrw LWKEN @ 0xC9; /* LMIWU enable register */ 00CA #pragma portrw LWKPND @ 0xCA; /* LMIWU pending register */ #endif /* __COP8C_H */ #include #ifndef __COP8_ISR_H 0008 #define __COP8_ISR_H /* * COP8C Code Development System * basic interrupt library routines * COP8_ISR.C * This code may be adapted for any purpose * when used with the COP8C Code Development * System. No warranty is implied or given * as to their usability for any purpose. * * (c) Copyright 2000 Byte Craft Limited * 421 King St.N., Waterloo, ON, Canada, N2J 4E4 * VOICE: 1 (519) 888 6911 * FAX : 1 (519) 746 6751 * email: support@bytecraft.com * * REVISION HISTORY * V0.90b AL 07/00 Initial Version. */ /* This library is used to simplify the use of * interrupts within C on all "COP8 BASIC FAMILY" * processors (processors without PUSH/POP instrustions * and no interrupt vector table) */ /* * possible conditions: * __BASIC_FAMILY * __NOLONG_MATH_ISR * __SREG */ #ifdef __BASIC_FAMILY #pragma vector __INT @ 0x00FF; /* use SaveContext and RestoreContext macros to save COP8 registers in the interrupt subroutines */ #ifdef __NO16BIT_NOMATH_ISR unsigned char temp_CONTEXT[5]; #asm MACRO __SAVE_16BIT_MATH ENDM MACRO __RESTORE_16BIT_MATH LD B,#(temp_CONTEXT+4) ENDM #endasm #else unsigned char temp_CONTEXT[13]; #asm expand MACRO __SAVE_16BIT_MATH LD B,#0 ;B points to MATH/16bit temps \_dec_next_context_save: LD A,[B+] ;save 0x00 - 0x07 to temp_CONTEXT[5-12] X A,[X+] IFBNE #8 JP \_dec_next_context_save ENDM MACRO __RESTORE_16BIT_MATH LD X,#(temp_CONTEXT+12) LD B,#7 ;B points to MATH/16bit temps \_dec_next_context_restore: LD A,[X-] ;save 0x00 - 0x07 to temp_CONTEXT[5-12] X A,[B-] IFBNE #0 JP \_dec_next_context_restore ENDM #endasm #endif /* __NO16BIT_NOMATH_ISR */ #asm MACRO ASM_SAVE_CONTEXT X A,temp_CONTEXT ;store temp_CONTEXT[0] = AREG LD A,X ;save X in A LD X,#temp_CONTEXT+1 ;load X with &temp_CONTEXT X A,[X+] ;store temp_CONTEXT[1] = X LD A,B X A,[X+] ;store temp_CONTEXT[2] = B LD A,PSW X A,[X+] ;store temp_CONTEXT[3] = PSW LD A,0xf0 X A,[X+] ;store temp_CONTEXT[4] = compiler temp __SAVE_16BIT_MATH ENDM MACRO ASM_RESTORE_CONTEXT __RESTORE_16BIT_MATH LD A,[B-] X A,0xf0 ;restore compiler temp LD A,[B] ADD A,[B] ;bit 7 into carry RBIT #7,$EF IFC SBIT #7,$EF ;set half carry RBIT #6,$EF IFBIT #6,[B] SC DRSZ B LD A,[B-] ;resotre B X A,B LD A,temp_CONTEXT+1 ;resotre X X A,X LD A,temp_CONTEXT ;resotre A ENDM #endasm #else /* __BASIC_FAMILY */ #ifdef __SREG #asm MACRO __SAVE_SREG LD A,S PUSH A ENDM MACRO __RESTORE_SREG POP A X A,S ENDM MACRO __CLEAR_SREG LD S,#0 ENDM #endasm #else /* __SREG */ #asm MACRO __RESTORE_SREG ENDM MACRO __SAVE_SREG ENDM MACRO __CLEAR_SREG ENDM #endasm #endif /* __SREG */ #ifdef __NO16BIT_NOMATH_ISR #asm MACRO __SAVE_16BIT_MATH ENDM MACRO __RESTORE_16BIT_MATH ENDM #endasm #else #asm MACRO __SAVE_16BIT_MATH __CLEAR_SREG LD B,#0 \_dec_next_context_save: LD A,[B+] ;save 0x00 - 0x07 on stack PUSH A IFBNE #8 JP \_dec_next_context_save ENDM MACRO __RESTORE_16BIT_MATH __CLEAR_SREG LD B,#7 ;B points to MATH/16bit temps \_dec_next_context_restore: POP A X A,[B-] ;restore 0x00 - 0x07 from stack IFBNE #0 JP \_dec_next_context_restore POP A X A,[B] ENDM #endasm #endif /* __NO16BIT_NOMATH_ISR */ #asm MACRO ASM_SAVE_CONTEXT PUSH A LD A,B PUSH A LD A,PSW PUSH A LD A,$F0 ;save compiler temp PUSH A __SAVE_SREG LD A,X PUSH A __SAVE_16BIT_MATH ENDM MACRO ASM_RESTORE_CONTEXT __RESTORE_16BIT_MATH POP A X A,X __RESTORE_SREG POP A X A,$F0 ;restore compiler temp POP A RC LD B,#PSW ;restore only C and HC from PSW IFBIT 7,A SBIT 7,[B] IFBIT 6,A SBIT 6,[B] POP A X A,B POP A ENDM #endasm #endif /* __BASIC_FAMILY */ /* use SaveContext and RestoreContext macros to save COP8 registers in the * interrupt subroutines */ 0009 #define SaveContext() #asm( ASM_SAVE_CONTEXT) 000A #define RestoreContext() #asm( ASM_RESTORE_CONTEXT) #endif /* __COP8_ISR_H */ /* figure_e */ 0008 int global_variable; void __INT(void) { SaveContext(); 0200 67 PUSHA 0201 9D FE LD A,B 0203 67 PUSHA 0204 9D EF LD A,0EF 0206 67 PUSHA 0207 9D F0 LD A,0F0 0209 67 PUSHA 020A 9D FF LD A,S 020C 67 PUSHA 020D 9D FC LD A,X 020F 67 PUSHA 0210 DF 00 LD S,#000 0212 5F LD B,#00 0213 AA LD A,[B+] 0214 67 PUSHA 0215 48 FC IFBNE 08 077F int var_in_interrupt; 0217 9F 7F LD B,#07F var_in_interrupt++; 0219 DF 07 LD S,#007 021B A6 X A,[B] 021C 8A INCA 021D A6 X A,[B] RestoreContext(); 021E DF 00 LD S,#000 0220 58 LD B,#07 0221 8C POPA 0222 A3 X A,[B-] 0223 40 FC IFBNE 00 0225 8C POPA 0226 A6 X A,[B] 0227 8C POPA 0228 9C FC X A,X 022A 8C POPA 022B 9C FF X A,S 022D 8C POPA 022E 9C F0 X A,0F0 0230 8C POPA 0231 A0 RC 0232 9F EF LD B,#0EF 0234 60 80 ANDSZ A,#080 0236 7F SBIT 07,[B] 0237 60 40 ANDSZ A,#040 0239 7E SBIT 06,[B] 023A 8C POPA 023B 9C FE X A,B 023D 8C POPA 023E 8E RET } /* figure_e */ /* figure_d */ void function1(void) { 0779 0778 0777 int a,b,c; 023F 8E RET } void function2(void) { 077C 077B 077A int a,b,c; 0240 FE JP 0023F function1(); } void function3(void) { 077C 077B 077A int a,b,c; 0241 8E RET } /* figure_d */ void function4(char a,b,c) 077C 077B 077A { 0242 8E RET } void main(void) { 077F 077E 077D int a,b,c; 0243 32 3F JSR 0023F function1(); 0245 32 40 JSR 00240 function2(); 0247 32 41 JSR 00241 function3(); /* figure_f */ 0249 DF 07 LD S,#007 024B 9F 7C LD B,#07C 024D 9B 01 LD [B-],#001 024F 9B 02 LD [B-],#002 0251 9E 03 LD [B],#003 0253 32 42 JSR 00242 function4(1,2,3); /* figure_f */ 0255 FF JP 00255 while(1); } #ifndef __COP8_ISR_C 000C #define __COP8_ISR_C /* * COP8C Code Development System * basic interrupt library routines * COP8_ISR.C * This code may be adapted for any purpose * when used with the COP8C Code Development * System. No warranty is implied or given * as to their usability for any purpose. * * (c) Copyright 2000 Byte Craft Limited * 421 King St.N., Waterloo, ON, Canada, N2J 4E4 * VOICE: 1 (519) 888 6911 * FAX : 1 (519) 746 6751 * email: support@bytecraft.com * * REVISION HISTORY * V0.90b AL 07/00 Initial Version. */ /* These pragma directives put a 'JMPL __INT' at the * interrup vector (0x00FF) if the function __INT is * defined*/ #ifdef __BASIC_FAMILY #ifdef __INT #if __INT != 0xff #pragma ECON @ 0xff = 0xAD; #pragma ECON @ 0x100 = __INT>>8; #pragma ECON @ 0x101 = __INT; #endif #endif /* __INT */ #endif /* __BASIC_FAMILY */ #endif /* __COP8_ISR_C */ #endif /* __COP8C_C */ __MAIN: 0000 DD 6F LD SP,#06F 0002 AC 02 43 JMPL 00243 SYMBOL TABLE LABEL VALUE LABEL VALUE ADBSY 0000 ADCH0 0004 ADCH1 0005 ADCH2 0006 ADCH3 0007 ADMOD 0003 ADRSLTH 00CC ADRSLTL 00CD ATTN 0002 B 00FE BAUD 00BD BD 0004 BREG Reg 00FE BRK 0006 BUSY 0002 C 0006 CCKSEL 0004 CHL0 0003 CHL1 0004 CNTRL 00EE CODE_START 0200 DCEN 0005 DOE 0007 ENAD 00CB ENU 00BA ENUI 00BC ENUR 00BB ERI 0001 ERR 0002 ETDX 0005 ETI 0000 EXEN 0001 EXPND 0003 FE 0006 FLEX_FLASH 0001 FLEX_ROM 0000 GIE 0000 HALT_DISABLE 0002 HALT_ENABLE 0000 HC 0007 HSON 0006 HSTCR 00AF ICNTRL 00E8 IEDG 0002 INTERRUPT_BRANCH_VECTOR 00FF ISPAD 00A8 ISPADHI 00A9 ISPADLO 00A8 ISPKEY 00E2 ISPRD 00AA ISPWR 00AB ITMR 00CF ITSEL0 0000 ITSEL1 0001 ITSEL2 0002 LPEN 0006 LSON 0007 LWKEDG 00C8 LWKEN 00C9 LWKPND 00CA MSEL 0003 MUX 0002 OPTION_LOCATION 7FFF PE 0005 PEN 0007 PGMTIM 00E1 PORTA 00A0 PORTAC 00A1 PORTAD 00A0 PORTAP 00A2 PORTB 00A4 PORTBC 00A5 PORTBD 00A4 PORTBP 00A6 PORTC 00D8 PORTCC 00D9 PORTCD 00D8 PORTCP 00DA PORTD 00DC PORTDD 00DC PORTE 0090 PORTEC 0091 PORTED 0090 PORTEP 0092 PORTF 0094 PORTFC 0095 PORTFD 0094 PORTFP 0096 PORTG 00D4 PORTGC 00D5 PORTGD 00D4 PORTGP 00D6 PORTL 00D0 PORTLC 00D1 PORTLD 00D0 PORTLP 00D2 PSC 0001 PSEL0 0005 PSEL1 0006 PSR 00BE PSW 00EF RAM_BANK0_SIZE 0028 RAM_BANK0_START 0008 RAM_BANK1_SIZE 0080 RAM_BANK1_START 0100 RAM_BANK2_SIZE 0080 RAM_BANK2_START 0200 RAM_BANK3_SIZE 0080 RAM_BANK3_START 0300 RAM_BANK4_SIZE 0080 RAM_BANK4_START 0400 RAM_BANK5_SIZE 0080 RAM_BANK5_START 0500 RAM_BANK6_SIZE 0080 RAM_BANK6_START 0600 RAM_BANK7_SIZE 0080 RAM_BANK7_START 0700 RAM_REGISTERS_SIZE 000B RAM_REGISTERS_START 00F1 RBFL 0001 RBIT9 0003 RBUF 00B9 RCVG 0000 ROM_SIZE 8000 S 00FF SEC_DISABLE 0000 SEC_ENABLE 0020 SIOR 00E9 SL0 0000 SL1 0001 SP 00FD SSEL 0004 STACK_SIZE 0040 STP2 0007 T0EN 0004 T0PND 0005 T1C0 0004 T1C1 0005 T1C2 0006 T1C3 0007 T1ENA 0004 T1ENB 0000 T1PND 0005 T1PNDA 0005 T1PNDB 0001 T1RAHI 00ED T1RALO 00EC T1RBHI 00E7 T1RBLO 00E6 T2C0 0004 T2C1 0005 T2C2 0006 T2C3 0007 T2CNTRL 00C6 T2ENA 0002 T2ENB 0000 T2HS 0000 T2PNDA 0003 T2PNDB 0001 T2RAHI 00C3 T2RALO 00C2 T2RBHI 00C5 T2RBLO 00C4 T3C0 0004 T3C1 0005 T3C2 0006 T3C3 0007 T3CNTRL 00B6 T3ENA 0002 T3ENB 0000 T3HS 0001 T3PNDA 0003 T3PNDB 0001 T3RAHI 00B3 T3RALO 00B2 T3RBHI 00B5 T3RBLO 00B4 TBMT 0000 TBUF 00B8 TINTA 00AD TINTB 00AE TMR2HI 00C1 TMR2LO 00C0 TMR3HI 00B1 TMR3LO 00B0 TMRHI 00EB TMRLO 00EA VIS_OPCODE 00B4 WDSVR 00C7 WD_DISABLE 0004 WD_ENABLE 0000 X 00FC XBIT9 0005 XMTG 0001 XRCLK 0003 XTCLK 0002 __BCdirect 0001 __EXT 01FA __INT Fun 0200 __MAIN 0243 __MICRO 01F2 __PORTL 01E2 __RESET 0000 __STARTUP Fun 0000 __SWI 01FE __TIMERT0 01F8 __TIMERT1A 01F6 __TIMERT1B 01F4 __TIMERT2A 01EA __TIMERT2B 01E8 __TIMERT3A 01E6 __TIMERT3B 01E4 __UARTR 01EE __UARTT 01EC __VIS 01E0 __longAC Reg 0002 __longIX Reg 0000 bank0 0001 bank1 0002 bank2 0003 bank3 0004 bank4 0005 bank5 0006 bank6 0007 bank7 0008 function1 Fun 023F function2 Fun 0240 function3 Fun 0241 function4 Fun 0242 global_variable Reg 0008 main Fun 0243 register 0009 uWEN 0002 uWPND 0003 REGISTER USAGE MAP ('X' = Used, '-' = Unused) 0000 : --------X------- ---------------- ---------------- XXXXXXXXXXXXXXXX 0040 : XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX ---------------- 0080 : ---------------- ---------------- ---------------- ---------------- 00C0 : ---------------- ---------------- ---------------- ---------------- 0100 : ---------------- ---------------- ---------------- ---------------- 0140 : ---------------- ---------------- ---------------- ---------------- 0180 : ---------------- ---------------- ---------------- ---------------- 01C0 : ---------------- ---------------- ---------------- ---------------- RAM USAGE MAP 0000 __longIX signed long 0002 __longAC signed long 00FE BREG unsigned char 00FC X portrw 00FD SP portrw 00FE B portrw 00FF S portrw 0090 PORTE portrw 0090 PORTED portrw 0091 PORTEC portrw 0092 PORTEP portr 0094 PORTF portrw 0094 PORTFD portrw 0095 PORTFC portrw 0096 PORTFP portr 00A0 PORTA portrw 00A0 PORTAD portrw 00A1 PORTAC portrw 00A2 PORTAP portr 00A4 PORTB portrw 00A4 PORTBD portrw 00A5 PORTBC portrw 00A6 PORTBP portr 00AD TINTA portr 00AE TINTB portr 00AF HSTCR portrw 00D0 PORTL portrw 00D0 PORTLD portrw 00D1 PORTLC portrw 00D2 PORTLP portr 00D4 PORTG portrw 00D4 PORTGD portrw 00D5 PORTGC portrw 00D6 PORTGP portr 00D8 PORTC portrw 00D8 PORTCD portrw 00D9 PORTCC portrw 00DA PORTCP portr 00DC PORTD portrw 00DC PORTDD portrw 00EE CNTRL portrw 00EF PSW portrw 00E8 ICNTRL portrw 00EA TMRLO portrw 00EB TMRHI portrw 00EC T1RALO portrw 00ED T1RAHI portrw 00E6 T1RBLO portrw 00E7 T1RBHI portrw 00C6 T2CNTRL portrw 00C0 TMR2LO portrw 00C1 TMR2HI portrw 00C2 T2RALO portrw 00C3 T2RAHI portrw 00C4 T2RBLO portrw 00C5 T2RBHI portrw 00B6 T3CNTRL portrw 00B0 TMR3LO portrw 00B1 TMR3HI portrw 00B2 T3RALO portrw 00B3 T3RAHI portrw 00B4 T3RBLO portrw 00B5 T3RBHI portrw 00E9 SIOR portrw 00CF ITMR portrw 00CB ENAD portrw 00CD ADRSLTL portrw 00CC ADRSLTH portrw 00A8 ISPAD portrw 00A8 ISPADLO portrw 00A9 ISPADHI portrw 00AA ISPRD portrw 00AB ISPWR portrw 00E1 PGMTIM portrw 00E2 ISPKEY portrw 00B8 TBUF portrw 00B9 RBUF portrw 00BA ENU portrw 00BB ENUR portrw 00BC ENUI portrw 00BD BAUD portrw 00BE PSR portrw 00C7 WDSVR portrw 00C8 LWKEDG portrw 00C9 LWKEN portrw 00CA LWKPND portrw 0008 global_variable signed char 077F var_in_interrupt signed char 0200 023D 0779 a signed char 023F 023E 0778 b signed char 023F 023E 0777 c signed char 023F 023E 077C a signed char 0240 0240 077B b signed char 0240 0240 077A c signed char 0240 0240 077C a signed char 0241 0240 077B b signed char 0241 0240 077A c signed char 0241 0240 077F a signed char 0243 0255 077E b signed char 0243 0255 077D c signed char 0243 0255 LOCAL RAM USAGE FROM 0780 TO 077F ROM USAGE MAP 0000 to 0004 00FF to 0100 0200 to 0255 Total ROM used 005D (93) Errors : 0 Warnings : 0